SH7616 datasheet(156/935 Pages) RENESAS

156 / 935 page

Section 4 Exception Handling

Rev. 2.00 Mar 09, 2006 page 130 of 906

REJ09B0292-0200

2. External vector number fetches can be performed without using the auto-vector

numbers in this table.

3. The vector numbers and vector table address offsets for each on-chip peripheral

module interrupt are given table 5.4, Interrupt Exception Vectors and Priorities, in

section 5, Interrupt Controller.

4. Vector numbers are set in the on-chip vector number register. See section 5.3, Register

Descriptions, in section 5, Interrupt Controller, and section 11, Direct Memory Access

Controller, for more information.

5. The same vector number, 10, is generated for a DMAC DMA address error and an E-

DMAC DMA address error. (See table 4.3 (a).)

Both the address error flag (AE) in the DMAC’s DMA operation register (DMAOR) and

the address error control bit (AEC) in the E-DMAC’s E-DMAC operation control register

(EDOCR) must therefore be read in the exception service routine to determine which

DMA address error has occurred.

Table 4.4

Calculating Exception Vector Table Addresses

Exception Source

Vector Table Address Calculation

Power-on reset

Manual reset

(Vector table address) = (vector table address offset)

= (vector number)

× 4

Other exception handling

(Vector table address) = VBR + (vector table address offset)

= VBR + (vector number)

× 4

Note: VBR: Vector base register

Vector table address offset: See table 4.3.

Vector number: See table 4.3.

SH7616 Datasheet(PDF) 156 Page - Renesas Technology Corp