SH7616 datasheet(155/935 Pages) RENESAS

155 / 935 page

Section 4 Exception Handling

Rev. 2.00 Mar 09, 2006 page 129 of 906

REJ09B0292-0200

Table 4.3 (b) Exception Processing Vector Table (IRQ Mode)

Exception Source

Vector

Number

Vector Table Address

Offset

Vector Addresses

Interrupt

IRQ0

64*

H'00000100–H'00000103

IRQ1

65*

H'00000104–H'00000107

IRQ2

66*

H'00000108–H'0000010B

IRQ3

67*

H'0000010C–H'0000010F

On-chip

peripheral

module*

127*

H'00000000–H'00000003

H'000001FC–H'000001FF

Table 4.3 (c) Exception Processing Vector Table (IRL Mode)

Exception Source

Vector

Number

Vector Table Address

Offset

Vector Addresses

Interrupt

IRL1*

64*

H'00000100–H'00000103

VBR + (vector

IRL2*

65*

H'00000104–H'00000107

number

× 4)

IRL3*

IRL4*

66*

H'00000108–H'0000010B

IRL5*

IRL6*

67*

H'0000010C–H'0000010F

IRL7*

IRL8*

68*

H'00000110–H'00000113

IRL9*

IRL10*

69*

H'00000114–H'00000117

IRL11*

IRL12*

70*

H'00000118–H'0000011B

IRL13*

IRL14*

71*

H'0000011C–H'0000011F

IRL15*

On-chip

peripheral

module*

0*4

127*

H'00000000–H'00000003

H'000001FC–H'000001FF

Notes: 1. When 1110 is input to the

IRL3, IRL2, IRL1, and IRL0 pins, an IRL1 interrupt results.

When 0000 is input, an IRL15 interrupt results.

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