SH7616 datasheet(157/935 Pages) RENESAS

157 / 935 page

Section 4 Exception Handling

Rev. 2.00 Mar 09, 2006 page 131 of 906

REJ09B0292-0200

4.2

Resets

4.2.1

Types of Resets

Resets have the highest priority of any exception source. There are two types of resets: manual

resets and power-on resets. As table 4.5 shows, both types of resets initialize the internal status of

the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in

manual resets, registers of all on-chip peripheral modules except the bus state controller (BSC),

user break controller (UBC), pin function controller (PFC), and frequency modification register

(FMR) are initialized. (Use the power-on reset when turning the power on.)

Table 4.5

Types of Resets

Conditions for

Transition to Reset Status

Internal Status

Type

NMI Pin

RES

RES Pin

CPU

On-Chip Peripheral Modules

Power-on reset

High

Low

Initialized

Manual reset

Low

Initialized

Initialized except for BSC, UBC,

PFC, and frequency modification

4.2.2

Power-On Reset

When the NMI pin is high and the

RES pin is driven low, the device performs a power-on reset.

For a reliable reset, the

RES pin should be kept low for at least the duration of the oscillation

settling time (when the PLL circuit is halted) or for 20tpcyc (when the PLL circuit is running).

During a power-on reset, the CPU’s internal state and all on-chip peripheral module registers are

initialized. See appendix B, Pin States, for the state of individual pins in the power-on reset state.

In a power-on reset, power-on reset exception handling starts when the NMI pin is kept high and

the

RES pin is first driven low for a set period of time and then returned to high. The CPU will

then operate as follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3–I0) of

the status register (SR) are set to H'F (1111).

4. The values fetched from the exception vector table are set in the program counter (PC) and

stack pointer (SP), and the program begins executing.

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