SH7616 datasheet(159/935 Pages) RENESAS

159 / 935 page

Section 4 Exception Handling

Rev. 2.00 Mar 09, 2006 page 133 of 906

REJ09B0292-0200

Table 4.6

Bus Cycles and Address Errors

Bus Cycle

Type

Bus

Master

Bus Cycle Description

Address Errors

Instruction CPU

Instruction fetched from even address

None (normal)

fetch

Instruction fetched from odd address

Address error

occurs

Instruction fetched from other than on-chip peripheral

module space

None (normal)

Instruction fetched from on-chip peripheral module

space

Address error

occurs

Data

CPU or

Word data accessed from even address

None (normal)

read/write DMAC,

E-DMAC

Word data accessed from odd address

Address error

occurs

Longword data accessed from a longword boundary

None (normal)

Longword data accessed from other than a longword

boundary

Address error

occurs

Access of cache purge space, address array read/write

space, on-chip peripheral module space, or

synchronous DRAM mode setting space by PC-relative

addressing

Address error

occurs

Access of cache purge space, address array read/write

space, data array read/write space, on-chip peripheral

module space, or synchronous DRAM mode setting

space by a TAS.B instruction

Address error

occurs

Byte, word, or longword data accessed in on-chip

peripheral module space at addresses H'FFFFFC00 to

H'FFFFFCFF

None (normal)

Longword data accessed in on-chip peripheral module

space at addresses H'FFFFFE00 to H'FFFFFEFF

Address error

occurs

Word or byte data accessed in on-chip peripheral

module space at addresses H'FFFFFE00 to

H'FFFFFEFF

None (normal)

Byte data accessed in on-chip peripheral module space

at addresses H'FFFF0000 to H'FFFFF0FF or

H'FFFFFF00 to H'FFFFFFFF

Address error

occurs

Word or longword data accessed in on-chip peripheral

module space at addresses H'FFFF0000 to

H'FFFFF0FF or H'FFFFFF00 to H'FFFFFFFF

None (normal)

Notes: 1. Address errors do not occur during the synchronous DRAM mode register write cycle.

2. 16-byte DMAC transfers use longword accesses.

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