SH7616 datasheet(163/935 Pages) RENESAS

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Section 4 Exception Handling

Rev. 2.00 Mar 09, 2006 page 137 of 906

REJ09B0292-0200

4.5

Exceptions Triggered by Instructions

4.5.1

Instruction-Triggered Exception Types

Exception handling can be triggered by a trap instruction, general illegal instruction or illegal slot

instruction, as shown in table 4.9.

Table 4.9

Types of Exceptions Triggered by Instructions

Type

Source Instruction

Comment

Trap instruction

TRAPA

—

Illegal slot

instruction

Undefined code placed

immediately after a delayed

branch instruction (delay slot)

and instructions that rewrite the

Delayed branch instructions: JMP, JSR,

BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

Instructions that rewrite the PC: JMP, JSR,

BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF

General illegal

instruction

Undefined code anywhere

besides in a delay slot

—

4.5.2

Trap Instructions

When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU

operates as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the TRAPA instruction.

3. The exception service routine start address is fetched from the exception vector table entry that

corresponds to the vector number specified by the TRAPA instruction. That address is jumped

to and the program starts executing. The jump that occurs is not a delayed branch.

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