SH7616 datasheet(162/935 Pages) RENESAS

162 / 935 page

Section 4 Exception Handling

Rev. 2.00 Mar 09, 2006 page 136 of 906

REJ09B0292-0200

4.4.2

Interrupt Priority Levels

The interrupt priority order is predetermined. When multiple interrupts occur simultaneously, the

interrupt controller (INTC) determines their relative priorities and begins exception handling

accordingly.

The priority order of interrupts is expressed as priority levels 0–16, with priority 0 the lowest and

priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always

accepted. The user break interrupt priority level is 15 and IRL interrupts have priorities of 1–15.

On-chip peripheral module interrupt priority levels can be set freely using the INTC’s interrupt

priority level setting registers A–E (IPRA–IPRE) as shown in table 4.8. The priority levels that

can be set are 0–15. Level 16 cannot be set. For more information on IPRA–IPRE, see sections

5.3.1, Interrupt Priority Level Setting Register A (IPRA), to 5.3.5, Interrupt Priority Level Setting

Table 4.8

Interrupt Priority Order

Type

Priority Level Comment

NMI

Fixed priority level. Cannot be masked

User break

Fixed priority level

H-UDI

Fixed priority level

IRL

1–15

Set with

IRL3–IRL0 pins

IRQ

0–15

Set with interrupt priority level setting register C

(IPRC)

On-chip peripheral module

0–15

Set with interrupt priority level setting registers A, B,

D, and E (IPRA, IPRB, IPRD, IPRE)

4.4.3

Interrupt Exception Handling

When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI

is always accepted, but other interrupts are only accepted if they have a priority level higher than

the priority level set in the interrupt mask bits (I3–I0) of the status register (SR).

When an interrupt is accepted, exception handling begins. In interrupt exception handling, the

CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted

interrupt is written to SR bits I3–I0. For NMI, however, the priority level is 16, but the value set in

I3–I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the

exception vector table for the accepted interrupt, that address is jumped to and execution begins.

For more information about interrupt exception handling, see section 5.4, Interrupt Operation.

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