DS26521 datasheet(162/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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RRTS3 (T1 Mode)

Receive Real-Time Status Register 3

0B2h

Bit #

Name

—

LORC

LSP

LDN

LUP

Default

Note: All bits in this register are real-time (not latched). See RRTS3 for E1 mode.

Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel

time.

Bit 2: Spare Code Detected Condition (LSP). Set when the spare code as defined in the T1RSCD1:T1RSCD2

registers is being received.

Bit 1: Loop-Down Code Detected Condition (LDN). Set when the loop-down code as defined in the

T1RDNCD1:T1RDNCD2 register is being received.

Bit 0: Loop-Up Code Detected Condition (LUP). Set when the loop-up code as defined in the

T1RUPCD1:T1RUPCD2 register is being received.

RRTS3 (E1 Mode)

Receive Real-Time Status Register 3

0B2h

Bit #

Name

—

LORC

—

V52LNK

RDMA

Default

Note: All bits in this register are real-time (not latched). See RRTS3 for T1 mode.

Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel

time.

Bit 1: V5.2 Link Detected Condition (V52LNK). Set on detection of a V5.2 link identification signal (G.965).

Bit 0: Receive Distant MF Alarm Condition (RDMA). Set when bit 6 of time slot 16 in frame 0 has been set for

two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.

DS26521 Datasheet(PDF) 162 Page - Maxim Integrated Products