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DS26521 Datasheet(PDF) 166 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 166 Page - Maxim Integrated Products |
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166 / 258 page  DS26521 Single T1/E1/J1 Transceiver 166 of 258 Register Name: RGCCS1, RGCCS2, RGCCS3, RGCCS4 Register Description: Receive Gapped-Clock Channel Select Registers 1 to 4 Register Address: 0CCh, 0CDh, 0CEh, 0CFh Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RGCCS1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 RGCCS2 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 RGCCS3 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 (F-bit) RGCCS4* (E1 Mode Only) Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receive Gapped Clock Channel Select Bits for Channels 1 to 32 (CH[1:32]). 0 = no clock is present on RCHCLK during this channel time 1 = force a clock on RCHCLK during this channel time. The clock will be synchronous with RCLK if the elastic store is disabled, and synchronous with RSYSCLK if the elastic store is enabled. *Note that RGCCS4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on RCHCLK for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is generated on RCHCLK during the F-bit time: RGCCS4.0 = 0, do not generate a clock during the F-bit. RGCCS4.0 = 1, generate a clock during the F-bit. In this mode, RGCCS4.1:RGCCS4.7 should be set to 0. Register Name: RCICE1, RCICE2, RCICE3, RCICE4 Register Description: Receive Channel Idle Code Enable Registers 1 to 4 Register Address: 0D0h, 0D1h, 0D2h, 0D3h Bit # (MSB) 7 6 5 4 3 2 1 0 (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RCICE1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 RCICE2 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 RCICE3 Name CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 RCICE4 (E1 Mode Only) Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receive Channel Idle Code Insertion Control Bits for Channels 1 to 32 (CH[1:32]). 0 = do not insert data from the Idle Code Array into the receive data stream 1 = insert data from the Idle Code Array into the receive data stream |
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