DS26521 datasheet(163/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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RRTS5

Receive Real-Time Status Register 5 (HDLC)

0B4h

Bit #

Name

—

PS2

PS1

PS0

—

RHWM

RNE

Default

Note: All bits in this register are real time.

Bits 6 to 4: Receive Packet Status (PS[2:0]). These are real-time bits indicating the status as of the last read of

the receive FIFO.

PS2

PS1

PS0

PACKET STATUS

In Progress: End of message has not yet been reached.

Packet OK: Packet ended with correct CRC codeword.

CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword.

Abort: Packet ended because an abort signal was detected (7 or more ones in a row).

Overrun: HDLC controller terminated reception of packet because receive FIFO is full.

Bit 1: Receive FIFO Above High Watermark Condition (RHWM). Set when the receive 64-byte FIFO fills beyond

the high watermark as defined by the Receive HDLC FIFO Control register (RHFC). This is a real-time bit.

Bit 0: Receive FIFO Not Empty Condition (RNE). Set when the receive 64-byte FIFO has at least one byte

available for a read. This is a real-time bit.

RHPBA

Receive HDLC Packet Bytes Available Register

0B5h

Bit #

Name

RPBA6

RPBA5

RPBA4

RPBA3

RPBA2

RPBA1

RPBA0

Default

Bit 7: Message Status (MS).

0 = Bytes indicated by RPBA[6:0] are the end of a message. Host must check the HDLC status register for

details.

1 = Bytes indicated by RPBA[6:0] are the beginning or continuation of a message. The host does not need

to check the HDLC status. The MS bit returns to a value of 1 when the Rx HDLC FIFO is empty.

Bits 6 to 0: Receive FIFO Packet Bytes Available Count (RPBA[6:0]). RPBA0 is the LSB.

DS26521 Datasheet(PDF) 163 Page - Maxim Integrated Products

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