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DS26521 Datasheet(PDF) 240 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 240 Page - Maxim Integrated Products |
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240 / 258 page ![]() DS26521 Single T1/E1/J1 Transceiver 240 of 258 12.1.2 SPI Bus Mode Table 12-2. SPI Bus Mode Timing (See Note 1, Figure 12-5.) SYMBOL (2) CHARACTERISTIC (3) SYMBOL MIN MAX UNITS Operating Frequency Slave fBUS(S) — 4 MHz t1 Cycle Time: Slave tCYC(S) 250 — ns t2 Enable Lead Time tLEAD(S) 15 — ns t3 Enable Lag Time tLAG(S) 15 — ns t4 Clock (CLK) High Time Slave tCLKH(S) t5 Clock (CLK) Low Time Slave tCLKL(S) t6 Data Setup Time (Inputs) Slave tSU(S) 5 — ns t7 Data Hold Time (Inputs) Slave tH(S) 15 — ns t8 Disable Time, Slave (4) tDIS(S) — 25 ns t9 Data Valid Time, After Enable Edge Slave (5) tV(S) — 40 ns t10 Data Hold Time, Outputs, After Enable Edge Slave tHD(S) 5 — ns Note 1: The timing parameters in this table are guaranteed by design (GBD). Note 2: Symbols refer to dimensions in Figure 12-5. Note 3: 100pF load on all SPI pins. Note 4: Hold time to high-impedance state. Note 5: With 100pF on all SPI pins. |
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