GX1 datasheet(233/247 Pages) NSC

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Instruction Set (Continued)

Instruction Issues for Instruction Set Summary

Issues a through c apply to real address mode only:

This is a protected mode instruction. Attempted execu-

tion in real mode will result in exception 6 (invalid

opcode).

Exception 13 fault (general protection) will occur in real

mode if an operand reference is made that partially or

fully extends beyond the maximum CS, DS, ES, FS, or

GS segment limit (FFFFH). Exception 12 fault (stack

segment limit violation or not present) will occur in real

mode if an operand reference is made that partially or

fully extends beyond the maximum SS limit.

This instruction may be executed in real mode. In real

mode, its purpose is primarily to initialize the CPU for

protected mode.

d. -

Issues e through g apply to real address mode and pro-

tected virtual address mode:

An exception may occur, depending on the value of the

operand.

LOCK# is automatically asserted, regardless of the

presence or absence of the LOCK prefix.

LOCK# is asserted during descriptor table accesses.

Issues h through r apply to protected virtual address mode

only:

Exception 13 fault will occur if the memory operand in

CS, DS, ES, FS, or GS cannot be used due to either a

segment limit violation or an access rights violation. If

a stack limit is violated, an exception 12 occurs.

For segment load operations, the CPL, RPL, and DPL

must agree with the privilege rules to avoid an excep-

tion 13 fault. The segment’s descriptor must indicate

“present” or exception 11 (CS, DS, ES, FS, GS not

present). If the SS register is loaded and a stack

segment not present is detected, an exception 12

occurs.

All segment descriptor accesses in the GDT or LDT

made by this instruction will automatically assert

LOCK# to maintain descriptor integrity in multipro-

cessor systems.

JMP, CALL, INT, RET, and IRET instructions referring

to another code segment will cause an exception 13, if

an applicable privilege rule is violated.

An exception 13 fault occurs if CPL is greater than 0 (0

is the most privileged level).

m. An exception 13 fault occurs if CPL is greater than

IOPL.

The IF bit of the Flags register is not updated if CPL is

greater than IOPL. The IOPL and VM fields of the

Flags register are updated only if CPL = 0.

The PE bit of the MSW (CR0) cannot be reset by this

instruction. Use MOV into CR0 if desiring to reset the

PE bit.

Any violation of privilege rules as apply to the selector

operand does not cause a Protection exception,

rather, the zero flag is cleared.

If the processor’s memory operand violates a segment

limit or segment access rights, an exception 13 fault

will occur before the ESC instruction is executed. An

exception 12 fault will occur if the stack limit is violated

by the operand’s starting address.

ThedestinationofaJMP, CALL,INT,RET,orIRET

must be in the defined limit of a code segment or an

exception 13 fault will occur.

Issue s applies to National Semiconductor-specific SMM

instructions:

All memory accesses to SMM space are non-cache-

able. An invalid opcode exception 6 occurs unless SMI

is enabled and SMAR size > 0, and CPL = 0 and

[SMAC is set or if in an SMI handler].

Issue t applies to cache invalidation instruction with the

cache operating in write-back mode:

The total clock count is the clock count shown plus the

number of clocks required to write all “modified” cache

lines to external memory.

GX1 Datasheet(PDF) 233 Page - National Semiconductor (TI)

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