48SWTQFN-EP datasheet(19/103 Pages) MAXIM

19 / 103 page

MAX9288/MAX9290

3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

www.maximintegrated.com

Maxim Integrated │ 19

NAME

FUNCTION

Mode Select with Internal Pulldown to EP. MS sets the control-link mode when CDS = high. Set MS

= low, to select base mode. Set MS = high to select the bypass mode. MS sets autostart mode when

CDS = low.

10, 23,

DVDD18

1.8V Digital Power Supply. Bypass DVDD18 to EP with 0.1µF and 0.001µF capacitors as close as

possible to the device with the smaller value capacitor closest to DVDD18.

GPIO1

Open-Drain, General-Purpose Input/Output, with Internal 60kΩ Pullup to IOVDD

EQS

Equalizer Select Input, with Internal Pulldown to EP. The state of EQS latches upon power-up or

when resuming from power-down mode (PWDN = low). Leave EQS open for 10.7dB equalizer boost

(EQTUNE = 1001). Connect EQS to IOVDD with a 30kΩ resistor for 5.2dB equalizer boost (EQTUNE =

0100).

RX/SDA

UART Receive/I2C Serial Data Input/Output, with Internal 30kΩ Pullup to IOVDD. Function is

determined by the state of I2CSEL at power-up. RX/SDA has an open-drain driver and requires a

pullup resistor.

RX: Input of the deserializer’s UART.

SDA: Data input/output of the deserializer’s I2C Master/Slave.

TX/SCL

UART Transmit/I2C Serial Clock Input/Output, with Internal 30kΩ Pullup to IOVDD. Function is

determined by the state of I2CSEL at power-up. TX/SCL has an open-drain driver and requires a pullup

resistor.

TX: Output of the deserializer’s UART.

SCL: Clock input/output of the deserializer’s I2C Master/Slave.

PWDN

Active-Low, Power-Down Input, with Internal Pulldown to EP. Set PWDN low to enter power-down

mode to reduce power consumption.

I2S/TDM Word-Select Input/Output. Powers up as an I2S output (deserializer provided clock). Set

AUDIOMODE bit = ‘1’ to change WS to an input with internal pulldown to GND and supply WS

externally (system provided clock).

SCK

I2S/TDM Serial-Clock Input/Output. Powers up as an I2S output (deserializer provided clock). Set

AUDIOMODE bit = ‘1’ to change SCK to an input with internal pulldown to GND and supply SCK

externally (system provided clock).

I2S/TDM Serial-Data Output. Disable I2S/TDM encoding to serial data to use SD as an additional

control/data output. Encrypted when HDCP is enabled.

ADD2/CNTL2

Address Selection Input/Auxiliary Control Signal Output, with Internal Pulldown to EP. Functions as

ADD2 input at power-up or when resuming from power-down mode (PWDN = low), and switches to

CNTL2 output automatically after power-up.

ADD2: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See

Table 1. Connect ADD2/CNTL2 to IOVDD with a 30kΩ resistor to set high or leave open to set low.

CNTL2: Used only in 32-bit and high-bandwidth mode (BWS = high, open). CNTL2 is mapped from the

GMSL serializer’s CNTL2 or DIN28 input.

Pin Description (continued)

48SWTQFN-EP Datasheet(PDF) 19 Page - Maxim Integrated Products

48SWTQFN-EP Datasheet(HTML) 19 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL