SC1100 datasheet(264/348 Pages) NSC

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264

Revision 1.1

Core Logic Module (Continued)

Offset 10Ch-10Fh

HceStatus Register (R/W)

Reset Value = 00000000h

31:8

Reserved. Read/Write 0s.

Parity. Indicates parity error on keyboard/mouse data.

Timeout. Used to indicate a time-out

AuxOutputFull. IRQ12 is asserted whenever this bit is set to 1 and OutputFull is set to 1 and the IRQEn bit is set.

Inhibit Switch. This bit reflects the state of the keyboard inhibit switch and is set if the keyboard is NOT inhibited.

CmdData. The HC will set this bit to 0 on an I/O write to port 60h and on an I/O write to port 64h the HC will set this bit to 1.

Flag. Nominally used as a system flag by software to indicate a warm or cold boot.

InputFull. Except for the case of a Gate A20 sequence, this bit is set to 1 on an I/O write to address 60h or 64h. While this

bit is set to 1 and emulation is enabled, an emulation interrupt condition exists.

OutputFull. The HC will set this bit to 0 on a read of I/O port 60h. If IRQEn is set and AuxOutputFull is set to 0 then an

IRQ1 is generated as long as this bit is set to 1. If IRQEn is set and AuxOutputFull is set to 1 then and IRQ12 will be gen-

erated a long as this bit is set to 1. While this bit is 0 and CharacterPending in HceControl is set to 1, an emulation interrupt

condition exists.

Note:

This register is the emulation side of the legacy Status register.

Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)

Bit

Description

SC1100 Datasheet(PDF) 264 Page - National Semiconductor (TI)