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SC1100 Datasheet(PDF) 304 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 304 Page - National Semiconductor (TI) |
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304 / 348 page  www.national.com 304 Revision 1.1 Electrical Specifications (Continued) 7.3.4 Sub-ISA Interface All output timing is guaranteed for 50 pF load, unless otherwise specified. The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011. Table 7-16. Output Signals Symbol Parameter Bus Width (Bits) Type Min (ns) Max (ns) Figure Comments tRD1 MEMR#/DOCR#/RD#/TRDE# Read active pulse width FE to RE 16 M 225 7-17 Standard tRD2 MEMR#/DOCR#/RD#/TRDE# Read active pulse width FE to RE 16 M 105 7-17 Zero wait state tRD3 IOR#/RD#/TRDE# Read active pulse width FE to RE 16 I/O 160 7-17 Standard tRD4 IOR#/MEMR#/DOCR#/RD#/TRDE# Read active pulse width FE to RE 8 M, I/O 520 7-17 Standard tRD5 IOR#/MEMR#/DOCR#/RD#/TRDE# Read active pulse width FE to RE 8 M, I/O 160 7-17 Zero wait state tRCU1 MEMR#/DOCR#/RD#/TRDE# inactive pulse width 16 M 103 7-17 tRCU2 MEMR#/DOCR#/RD#/TRDE# inactive pulse width 8M 163 7-17 tRCU3 IOR#/RD#/TRDE# inactive pulse width 8, 16 I/O 163 7-17 tWR1 MEMW#/WR# Write active pulse width FE to RE 16 M 225 7-18 Standard tWR2 MEMW#/DOCW#/WR# Write active pulse width FE to RE 16 M 105 7-18 Zero wait state tWR3 IOW#/WR# Write active pulse width FE to RE 16 I/O 160 7-18 Standard tWR4 IOW#/MEMW#/DOCW#/WR# Write active pulse width FE to RE 8 M, I/O 520 7-18 Standard tWR5 IOW#/MEMW#/DOCW#/WR# Write active pulse width FE to RE 8 M, I/O 160 7-18 Zero wait state tWCU1 MEMW#/WR#/DOCW# inactive pulse width 16 M 103 7-18 tWCU2 MEMW#/WR#/DOCW# inactive pulse width 8M 163 7-18 tWCU3 IOW#/WR# inactive pulse width 8, 16 I/O 163 7-18 tRDYH IOR#/MEMR#/RD#/DOCR#/IOW#/ MEMW#/WR#/DOCW# Hold after IOCHRDY RE 8, 16 M, I/O 120 7-17 7-18 tRDYA1 IOCHRDY valid after IOR#/MEMR#/ RD#/DOCR#/IOW#/MEMW#/WR#/ DOCW# FE 16 M, I/O 78 7-17 7-18 |
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