SC1100 datasheet(300/348 Pages) NSC

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300

Revision 1.1

Electrical Specifications (Continued)

Figure 7-12. PCICLK Timing and Measurement Points

tHIGH

0.4 VIO, p-to-p

(minimum)

0.6VIO

0.2VIO

0.5 VIO

0.4 VIO

0.3 VIO

tCYC

tLOW

PCICLK

Table 7-14. PCI Bus Timing Parameters

Symbol

Parameter

Min

Max

Unit

Comments

tVAL

PCICLK to Signal Valid Delay1,2,4 (on the bus)

211

tVAL(ptp)

PCICLK to Signal Valid Delay1,2,4 (point-to-point)

212

tON

Float to Active Delay1,3

2ns

tOFF

Active to Float Delay1,3

tSU

Input Setup Time to PCICLK4,5 (on the bus)

7ns

tSU(ptp)

Input Setup Time to PCICLK4,5

(point-to-point)

10,12

Input Hold Time from PCICLK5

0ns

tRST

PCIRST# Active Time After Power Stable6,3

1ms

tRST-CLK

PCIRST# Active Time After PCICLK Stable6,3

100

µs

tRST-OFF

PCIRST# Active to Output Float Delay3,6,7,

See the timing measurement conditions in Figure 7-14.

Minimum times are evaluated with same load used for slew rate measurement (as shown in note 3 of Table ); maximum

times are evaluated with the load circuits shown in Figure 7-13, for high-going and low-going edges respectively.

Not 100% tested.

REQ# and GNT# are point-to-point signals, and have different output valid delay and input setup times than do signals

on the bus. GNT# has a setup time of 10 ns; REQ# has a setup time of 12 ns. All other signals are sent via the bus.

See the timing measurement conditions in Figure 7-15.

PCIRST# is asserted and deasserted asynchronously with respect to PCICLK (see Figure 7-16).

All output drivers are asynchronously floated when PCIRST# is active.

SC1100 Datasheet(PDF) 300 Page - National Semiconductor (TI)

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