SC1100 datasheet(298/348 Pages) NSC

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298

Revision 1.1

Electrical Specifications (Continued)

7.3.3

PCI Bus

The SC1100 is compliant with PCI Bus Rev. 2.1 specifications. Relevant information from the PCI Bus specifications is pro-

vided below. Not all parameters in Table 7-12 are 100% tested. The parameters in this table are further described in Figure

7-11.

Figure 7-10. Testing Setup for Slew Rate and Minimum Timing

Table 7-12. AC Specifications

Symbol

Parameter

Min

Max

Unit

Comments

IOH(AC)

1, 2

Refer to the V/I curves in Figure 7-11. This specification does not apply to PCICLKO and PCIRST# which are system

outputs.

Maximum current requirements are met when drivers pull beyond the first step voltage. Equations which define these

maximum values (A and B) are provided with relevant diagrams in Figure 7-11. These maximum values are guaranteed

by design.

Switching Current

High

-12VIO

0 < VOUT ≤ 0.3VIO

-17.1(VIO-VOUT)mA

0.3VIO < VOUT < 0.9VIO

Equation A

(Figure 7-11)

0.7VIO < VOUT < VIO

Test Point2

-32VIO

VOUT = 0.7VIO

IOL(AC)

Switching Current

Low

16VIO

VIO > VOUT ≥ 0.6VIO

26.7VOUT

0.6VIO > VOUT > 0.1VIO

Equation B

(Figure 7-11)

0.18VIO>VOUT>0

Test Point2

38VIO

VOUT = 0.18VIO

ICL

Low Clamp Current

-25+(VIN+1)/0.015

-3 < VIN < -1

ICH

High Clamp Current

25+(VIN-VIO-1)/0.015

VIO+4 > VIN > VIO+1

SLEWR

Rise slew rate does not apply to open-drain outputs. This parameter is interpreted as the cumulative edge rate across

the specified range, according to the test circuit in Figure 7-10.

Output Rise Slew

Rate

V/ns

0.2VIO - 0.6VIO Load

SLEWF

Output Fall Slew Rate

V/ns

0.6VIO - 0.2VIO Load

Buffer

VCC

0.5" max.

1 K

Ω

1 K

Ω

10 pF

Output

SC1100 Datasheet(PDF) 298 Page - National Semiconductor (TI)

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