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SC1100 Datasheet(PDF) 316 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 316 Page - National Semiconductor (TI) |
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316 / 348 page  www.national.com 316 Revision 1.1 Electrical Specifications (Continued) Table 7-22. UltraDMA Data Burst Timing Requirements Symbol Parameter Mode 0 (ns) Mode 1 (ns) Mode 2 (ns) Min Max Min Max Min Max t2CYC Typical sustained average two cycle time 240 160 120 Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE) 235 156 117 tCYC Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) 114 75 55 tDS Data setup time (at recipient) 15 10 7 tDH Data hold time (at recipient) 5 5 5 tDVS Data valid setup time at sender (from data bus being valid until STROBE edge) 70 48 34 tDVH Data valid hold time at sender (from STROBE edge until data may become invalid) 666 tFS First STROBE time (for device to first negate IDE_IRDY[0:1] (DSTROBE[0:1]) from IDE_IOW[0:1]# (STOP[0:1]) during a data in burst) 0230 0200 0170 tLI Limited interlock time1 1. tUI, tMLI, and tLI indicate sender-to-recipient or recipient-to-sender interlocks, that is, one agent (either sender or recipi- ent) is waiting for the other agent to respond with a signal before proceeding. tUI is an unlimited interlock with no maxi- mum time value. tMLI is a limited time-out with a defined minimum. tLI is a limited time-out with a defined maximum. 0150 0150 0150 tMLI Interlock time with minimum1 20 20 20 tUI Unlimited interlock time1 000 tAZ Maximum time allowed for output drivers to release (from being asserted or negated) 10 10 10 tZAH Minimum delay time required for output drivers to assert or negate (from released state) 20 20 20 tZAD 000 tENV Envelope time (from IDE_DACK[0:1]# to IDE_IOW[0:1]# (STOP[0:1]) and IDE_IOR[0:1]# (HDMARDY[0:1]#) during data out burst initiation) 20 70 20 70 20 70 tSR STROBE to DMARDY time (if DMARDY# is negated before this long after STROBE edge, the recipient shall receive no more than one additional data WORD) 50 30 20 tRFS Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY#) 75 60 50 tRP Ready-to-pause time (time that recipient shall wait to ini- tiate pause after negating DMARDY#) 160 125 100 tIORDYZ Pull-up time before allowing IDE_IORDY[0:1] to be released 20 20 20 tZIORDY Minimum time device shall wait before driving IDE_IORDY[0:1] 000 TACK Setup and hold times for IDE_DACK[0:1]# (before asser- tion or negation) 20 20 20 TSS Time from STROBE edge to negation of IDE_DREQ[0:1] or assertion of IDE_IOW[0:1]# (STOP[0:1]) (when sender terminates a burst) 50 50 50 |
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