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SC1100 Datasheet(PDF) 106 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 106 Page - National Semiconductor (TI) |
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106 / 348 page ![]() www.national.com 106 Revision 1.1 SuperI/O Module (Continued) Table 4-32. Bank Selection Encoding BSR Bits Bank Selected 7 654 3210 0 xxx xxx x 0 1 0 xx xxx x 1 1 1 xx xx 1 x 1 1 1 xx xxx 1 1 1 110 0000 2 1 110 0100 3 Table 4-33. Bank 1 Register Map Offset Type Name 00h R/W LBGD(L). Legacy Baud Generator Divisor Port (Low Byte) 01h R/W LBGD(H). Legacy Baud Generator Divisor Port (High Byte) 02h --- RSVD. Reserved 03h W LCR1. Line Control R/W BSR1. Bank Select 04h-07h --- RSVD. Reserved 1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-32 on page 106. Table 4-34. Bank 2 Register Map Offset Type Name 00h R/W BGD(L). Baud Generator Divisor Port (Low Byte) 01h R/W BGD(H). Baud Generator Divisor Port (High Byte) 02h R/W EXCR1. Extended Control 1 03h R/W LCR/BSR. Link Control/Bank Select 04h R/W EXCR2. Extended Control 2 05h --- RSVD. Reserved 06h RO TXFLV. TX_FIFO Level 07h RO RXFLV. RX_FIFO Level Table 4-35. Bank 3 Register Map Offset Type Name 00h RO MRID. Module and Revision ID 01h RO SH_LCR. Shadow of LCR 02h RO SH_FCR. Shadow of FIFO Control 03h R/W LCR/BSR. Link Control/Bank Select 04h-07h --- RSVD. Reserved |
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