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SC1100 Datasheet(PDF) 108 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 108 Page - National Semiconductor (TI) |
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108 / 348 page  www.national.com 108 Revision 1.1 SuperI/O Module (Continued) 4.8.2 IR Communications Port (IRCP) Functionality This section describes the IRCP support registers. The IRCP functional block provides advanced, versatile serial communications features with IR capabilities. The IRCP also supports two DMA channels; the functional block can use either one or both of them. One channel is required for IR-based applications, since IR communication works in half duplex fashion. Two channels would normally be needed to handle high-speed full duplex IR based appli- cations. The IRCP signals are chosen via bit 6 of the PMR register (see Section 3.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 50). 4.8.2.1 IRCP Mode Register Bank Overview Eight register banks, each containing eight registers, con- trol IRCP operation. All registers use the same 8-byte address space to indicate offsets 00h through 07h. The BSR register selects the active bank and is common to all banks. See Figure 4-19. Figure 4-19. IRCP Register Bank Architecture Table 4-38. Bank 2 Bit Map Register Bits Offset Name 7 6543 21 0 00h BGD(L) BGD[7:0] (Low Byte) 01h BGD(H) BGD [15:8] (High Byte) 02h EXCR1 BTEST RSVD ETDLBK LOOP RSVD EXT_SL 03h LCR/BSR BKSE BSR[6:0] (Bank Select) 04h EXCR2 LOCK RSVD PRESL[1:0] RSVD 05h RSVD Reserved 06h TXFLV RSVD TFL[4:0] 07h RXFLV RSVD RFL[4:0] Table 4-39. Bank 3 Bit Map Register Bits Offset Name 765 43 21 0 00h MRID MID[3:0] RID[3:0] 01h SH_LCR BKSE SBRK STKP EPS PEN STB WLS[1:0] 02h SH_FCR RXFTH[1:0] TXFHT[1:0] RSVD TXSR RXSR FIFO_EN 03h LCR/BSR BKSE BSR[6:0] (Bank Select) 04h-07h RSVD RSVD Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Offset 07h Offset 06h Offset 05h Offset 04h LCR/BSR Offset 02h Offset 01h Offset 00h Common Register Throughout All Banks |
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