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SC1100 Datasheet(PDF) 107 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 107 Page - National Semiconductor (TI) |
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107 / 348 page ![]() Revision 1.1 107 www.national.com SuperI/O Module (Continued) Table 4-36. Bank 0 Bit Map Register Bits Offset Name 76 54 32 10 00h RXD RXD[7:0] (Receiver Data Bits) TXD TXD[7:0] (Transmitter Data Bits) 01h IER1 RSVD MS_IE LS_IE TXLDL_IE RXHDL_IE IER2 RSVD TXEMP_IE DMA_IE MS_IE LS_IE TXLDL_IE RXHDL_IE 02h EIR1 FEN[1:0] RSVD RXFT IPR1 IPR0 IPF EIR2 RSVD TXEMP_EV DMA_EV MS_EV LS_EV or TXHLT_EV TXLDL_EV RXHDL_EV FCR RXFTH[1:0] TXFTH[1:0] RSVD TXSR RXSR FIFO_EN 03h LCR3 BKSE SBRK STKP EPS PEN STB WLS[1:0] BSR3 BKSE BSR[6:0] (Bank Select) 04h MCR1 RSVD LOOP ISEN or DCDLP RILP RTS DTR MCR2 RSVD TX_DFR RSVD RTS DTR 05h LSR ER_INF TXEMP TXRDY BRK FE PE OE RXDA 06h MSR DCD RI DSR CTS DDCD TERI DDSR DCTS 07h SPR1 Scratch Data ASCR2 RSVD TXUR RXACT RXWDG RSVD S_OET RSVD RXF_TOUT 1. Non-Extended Mode. 2. Extended Mode. 3. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-32 on page 106. Table 4-37. Bank 1 Bit Map Register Bits Offset Name 76 54 32 10 00h LBGD(L) LBGD[7:0] (Low Byte) 01h LBGD(H) LBGD[15:8] (High Byte) 02h RSVD Reserved 03h LCR1 BKSE SBRK STKP EPS PEN STB WLS[1:0] BSR1 BKSE BSR[6:0] (Bank Select) 04h-07h RSVD Reserved 1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-32 on page 106. |
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