S5335 datasheet(147/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

147

Data Sheet

Single Cycle Pass-Thru Reads

A single cycle Pass-Thru read operation occurs when

a PCI initiator reads a single value from a Pass-Thru

region. PCI single cycle transfers consists of an

address phase and a one data phase. During the ad-

dress phase of the PCI transfer, the S5335 stores the

PCI address into the Pass-Thru Address Register

(APTA). If the S5335 determines that the address is

within one of its defined Pass-Thru regions, it indicates

to the Add-On that a write to the Pass-Thru Data Reg-

ister (APTD) is required.

Figure 85 shows a single cycle Pass-Thru read access

(Add-On write) using PTADR#. The Add-On reads

data from a source on the Add-On and writes it to the

APTD register.

Pass-Thru Burst Writes

A Pass-Thru burst write operation occurs when a PCI

initiator writes multiple values to a Pass-Thru region. A

PCI burst cycle consists of an address phase and mul-

tiple data phases. During the address phase of the

PCI transfer, the S5335 stores the PCI address into

the Pass-Thru Address Register (APTA). If the S5335

determines that the address is within one of its defined

Pass-Thru regions, it captures the PCI data into the

Pass-Thru Data Register (APTD). After the Add-On

completes each read from the Pass-Thru data register

(asserts PTRDY#), the next data phase is initiated.

Figure 86 shows a 6 data phase Pass-Thru burst write

(Add-On read). In this case, the Add-On asserts

PTADR# and then reads multiple data phases from the

S5335. This works well for Add-On logic which sup-

ports burst cycles. If the Add-On logic does not

support burst accesses, PTADR# may be pulsed

before each data phase. The S5335 automatically

increments the address in the APTA register during

PCI burst cycles. In this example PTRDY# is always

asserted, indicating Add-On logic is capable of accept-

ing data at a rate of one DWORD per clock cycle.

Clock 0:

PCI address information is stored in the S5335 Pass-Thru Address Register. The PCI cycle is recognized as an

access to Pass-Thru region 1. PTATN# is asserted by the S5335 to indicate a Pass-Thru access is occurring.

Clock 1:

Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid

when PTATN# is active and are sampled by the Add-On at the rising edge of clock 1.

PTBURST#

Deasserted. The access has a single data phase. PTNUM[1:0] 01. Indicates the PCI access was

to Pass-Thru region 1.

PTWR

Deasserted. The Pass-Thru access is a read.

PTBE[3:0]#

0h. Indicate the Pass-Thru access is 32-bits.

The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and SELECT#

inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3.

Clock 2:

This clock is required to avoid contention on the DQ bus. Time must be allowed after PTADR# is deasserted for

the DQ outputs to float before Add-On logic attempts to write to the Pass-Thru Data Register.

Clock 3:

SELECT#, byte enables, and the address inputs remain valid to write the Pass-Thru Data Register at offset 2Ch.

If WR# is asserted at the rising edge of clock 3, data on the DQ bus is latched into APTD.

If PTRDY# is asserted at the rising edge of clock 3, PTATN# is immediately deasserted and the Pass-Thru

access is completed at clock 4.

Clock 4:

If Add-On logic requires more time to write the Pass-Thru data register (slower memory or peripherals), PTRDY#

can be delayed, extending the cycle. PTRDY# asserted at the rising edge of clock 4 causes PTATN# to be imme-

diately deasserted and the Pass-Thru access is completed at clock 5.

Clock 5:

PTATN# and PTBURST# deasserted at the rising edge of clock 5 indicates the Pass-Thru access is complete.

The S5335 can accept new Pass-Thru accesses from the PCI bus at clock 6.

S5335 Datasheet(PDF) 147 Page - Applied Micro Circuits Corporation

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