7702 datasheet(112/217 Pages) RENESAS

112 / 217 page

TIMER A

7702/7703 Group User’s Manual

5–24

5.4 Event counter mode

Timer Ai interrupt

request bit

FFFF16

000016

Time

Count start bit “1”

“1”

n = Reload register’s contents

Cleared to “0” when interrupt request is accepted or cleared by software.

Set to “1” by software.

Starts counting.

Up-down bit “1”

Note: The above applies when the up-down bit’s contents are selected as the up-down switching factor (i.e., up-down

switching factor select bit = “0” ).

“0”

Set to “1” by software.

5.4.2 Operation in event counter mode

When the count start bit is set to “1,” the counter starts counting of the count source.

The counter counts the count source’s valid edges.

When the counter underflows or overflows, the reload register’s contents are reloaded and counting

continues.

The timer Ai interrupt request bit is set to “1” when the counter underflows or overflows in .

The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request

bit is cleared to “0” by software.

Figure 5.4.4 shows an example of operation in the event counter mode.

Fig. 5.4.4 Example of operation in event counter mode (without pulse output function and two-phase

pulse signal processing function)

7702 Datasheet(PDF) 112 Page - Renesas Technology Corp