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DS26521 Datasheet(PDF) 102 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 102 Page - Maxim Integrated Products |
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102 / 258 page ![]() DS26521 Single T1/E1/J1 Transceiver 102 of 258 Register Name GTCR1 Register Description: Global Transceiver Control Register 1 Register Address: 0F0h Bit # 7 6 5 4 3 2 1 0 Name — — RLOFLTS GIBOE — — GCLE GIPI Default 0 0 0 0 0 0 0 0 Bit 5: Receive Loss of Frame/Loss of Transmit Clock Indication Select (RLOFLTS). 0 = RLOF/LTC pin indicates framer receive loss of frame 1 = RLOF/LTC pin indicates framer loss of transmit clock Bit 4: Global IBO Enable (GIBOE). 0 = normal mode—IBO disabled 1 = IBO enabled Note: To enable IBO, this bit must be set, RIBOC.IBOEN must be set, and TIBOC.IBOEN must be set. Enabling IBO forces output pins (RSER and RSIG) to tri-state at the appropriate times. Bit 1: Global Counter Latch Enable (GCLE). A low-to-high transition on this bit will, when enabled, latch the framer performance monitor counters. Each framer can be independently enabled to accept this input. This bit must be cleared and set again to perform another counter latch. Bit 0: Global Interrupt Pin Inhibit (GIPI). 0 = Normal operation. Interrupt pin ( INTB) will toggle low on an unmasked interrupt condition. 1 = Interrupt inhibit. Interrupt pin ( INTB) is forced high (inactive) when this bit is set. |
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