DS26521 datasheet(103/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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GFCR

Description:

Global Framer Control Register

0F1h

Bit #

Name

—

BPCLK1

BPCLK0

RFLOSSFS

RFMSS

TCBCS

RCBCS

Default

Bits 5 and 4: Backplane Clock Select 1 and 0 (BPCLK[1:0]). These bits determine the clock frequency output on

the BPCLK pin.

BPCLK1

BPCLK0

BPCLK FREQUENCY

2.048MHz

4.096MHz

8.192MHz

16.384MHz

Bit 3: Receive Loss of Signal/Signaling Freeze Select (RLOSSFS). This bit controls the function of the

AL/RSIGF/FLOS pin. The receive LOS is further selected between framer LOS and LIU LOS by GTCR2.2.

0 = AL/RSIGF/FLOS pin outputs RLOS (receive loss)

1 = AL/RSIGF/FLOS pin outputs RSIGF (receive-signaling freeze)

Bit 2: Receive Frame/Multiframe Sync Select (RFMSS). This bit controls the function of the RMSYNC/RFSYNC

pin.

0 = RMSYNC/RFSYNC pin outputs RFSYNC (receive frame sync)

1 = RMSYNC/RFSYNC pin outputs RMSYNC (receive multiframe sync)

Bit 1: Transmit Channel Block/Clock Select (TCBCS). This bit controls the function of the TCHBLK/CLK pin.

0 = TCHBLK/CLK pin outputs TCHBLK (transmit channel block)

1 = TCHBLK/CLK pin outputs TCHCLK (transmit channel clock)

Bit 0: Receive Channel Block/Clock Select (RCBCS). This bit controls the function of the RCHBLK/CLK pin.

0 = RCHBLK/CLK pin outputs RCHBLK (receive channel block)

1 = RCHBLK/CLK pin outputs RCHCLK (receive channel clock)

GTCR2

Global Transceiver Control Register 2

0F2h

Bit #

Name

—

LOSS

TSSYNCIOSEL

—

Default

Bit 2: LOS Selection (LOSS). If this bit is set, the AL/RSIGF/FLOS pin can be driven with LIU loss. If reset, the

pins can be driven by framer LOS. The selection of whether to drive AL/RSIGF/FLOS pin with LOS (analog or

digital) or signalling freeze is controlled by GFCR.2.

Bit 1: Transmit System Synchronization I/O Select (TSSYNCIOSEL). If this bit is set to a 1, the TSSYNCIO is

an 8kHz output synchronous to the BPCLK. This “frame pulse” can be used in conjunction with the backplane clock

to provide IBO signals for a system backplane. If this bit is reset, TSSYNCIO is an input. An 8kHz frame pulse is

required for transmit synchronization and IBO operation.

DS26521 Datasheet(PDF) 103 Page - Maxim Integrated Products

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