DS26521 datasheet(143/258 Pages) MAXIM

143 / 258 page

DS26521 Single T1/E1/J1 Transceiver

143 of 258

RLS2 (E1 Mode)

Receive Latched Status Register 2

091h

Bit #

Name

—

CRCRC

CASRC

FASRC

RSA1

RSA0

RCMF

RAF

Default

Note: All bits in this register are latched. Bits 0 to 3 can cause interrupts. There is no associated real-time register. See RLS2 for T1 mode.

Bit 6: CRC Resync Criteria Met Event (CRCRC). Set when 915:1000 codewords are received in error.

Bit 5: CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are

received in error.

Bit 4: FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error.

Bit 3: Receive-Signaling All-Ones Event (RSA1). Set when the contents of time slot 16 contains less than three

zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.

Bit 2: Receive-Signaling All-Zeros Event (RSA0). Set when over a full MF, time slot 16 contains all zeros.

Bit 1: Receive CRC-4 Multiframe Event (RCMF). Set on CRC-4 multiframe boundaries This bit continues to be

set every 2ms on an arbitrary boundary if CRC-4 is disabled.

Bit 0: Receive Align Frame Event (RAF). Set approximately every 250

μs to alert the host that Si and Sa bits are

available in the RAF and RNAF registers.

DS26521 Datasheet(PDF) 143 Page - Maxim Integrated Products