DS26521 datasheet(145/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

145 of 258

RLS3 (E1 Mode)

Receive Latched Status Register 3

092h

Bit #

Name

LORCC

—

V52LNKC

RDMAC

LORCD

—

V52LNKD

RDMAD

Default

Note: All bits in this register are latched and can create interrupts. See RLS3 for T1 mode.

Bit 7: Loss of Receive Clock Clear (LORCC). Change of state indication. Set when an LORC condition has

cleared (falling edge detect of LORC)

Bit 5: V5.2 Link Detected Clear (V52LNKC). Change of state indication. Set when a V52LNK condition has

cleared (falling edge detect of V52LNK).

Bit 4: Receive Distant MF Alarm Clear (RDMAC). Change of state indication. Set when an RDMA condition has

cleared (falling edge detect of RDMA).

Bit 3: Loss of Receive Clock Detect (LORCD). Change of state indication. Set when the RCLK pin has not

transitioned for one channel time (rising edge detect of LORC).

Bit 1: V5.2 Link Detect (V52LNKD). Change of state indication. Set on detection of a V5.2 link identification signal.

(G.965). This is the rising edge detect of V52LNK.

Bit 0: Receive Distant MF Alarm Detect (RDMAD). Change of state indication. Set when bit 6 of time slot 16 in

frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This

is the rising edge detect of RDMA.

DS26521 Datasheet(PDF) 145 Page - Maxim Integrated Products