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DS26521 Datasheet(PDF) 148 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 148 Page - Maxim Integrated Products |
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148 / 258 page ![]() DS26521 Single T1/E1/J1 Transceiver 148 of 258 Register Name: RLS7 (T1 Mode) Register Description: Receive Latched Status Register 7 Register Address: 096h Bit # 7 6 5 4 3 2 1 0 Name — — RRAI-CI RAIS-CI RSLC96 RFDLF BC BD Default 0 0 0 0 0 0 0 0 Note: All bits in this register are latched and can create interrupts. See RLS7 for E1 mode. Bit 5: Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI pattern has been detected by the receiver. This bit is active in ESF framing mode only, and will set only if an RAI condition is being detected (RRTS1.3). When the host reads (and clears) this bit, it will set again each time the RAI-CI pattern is detected (approximately every 1.1 seconds). Bit 4: Receive AIS-CI Detect (RAIS-CI). Set when an AIS-CI pattern has been detected by the receiver. This bit will set only if an AIS condition is being detected (RRTS1.2). This is a latched bit that must be cleared by the host, and will set again each time the AIS-CI pattern is detected (approximately every 1.2 seconds). Bit 3: Receive SLC-96 Alignment Event (RSLC96). Set when a valid SLC-96 alignment pattern is detected in the Fs-bit stream, and the RSLCx registers have data available for retrieval. See Section 8.9.4.5 for more information. Bit 2: Receive FDL Register Full Event (RFDLF). Set when the 8-bit T1RFDL register is full. Useful for SLC-96 operation, or manual extraction of FDL data bits. See Section 8.9.5.4 for more information. Bit 1: BOC Clear Event (BC). Set when a valid BOC is no longer detected (with the disintegration filter applied). Bit 0: BOC Detect Event (BD). Set when a valid BOC has been detected (with the BOC filter applied). Register Name: RLS7 (E1 Mode) Register Description: Receive Latched Status Register 7 Register Address: 096h Bit # 7 6 5 4 3 2 1 0 Name — — — — — — Sa6CD SaXCD Default 0 0 0 0 0 0 0 0 Note: All bits in this register are latched and can create interrupts. See RLS7 for T1 mode. Bit 1: Sa6 Codeword Detect (Sa6CD). Set when a valid codeword (per ETS 300 233) is detected in the Sa6 bit positions. Bit 0: SaX Bit Change Detect (SaXCD). Set when a bit change is detected in the SaX bit position. The enabled SaX bits are selected by the E1RSAIMR register. |
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