DS26521 datasheet(147/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

147 of 258

RLS5

Receive Latched Status Register 5 (HDLC)

094h

Bit #

Name

—

ROVR

RHOBT

RPE

RPS

RHWMS

RNES

Default

Note: All bits in this register are latched and can cause interrupts.

Bit 5: Receive FIFO Overrun (ROVR). Set when the receive HDLC controller has terminated packet reception

because the FIFO buffer is full.

Bit 4: Receive HDLC Opening Byte Event (RHOBT). Set when the next byte available in the receive FIFO is the

first byte of a message.

Bit 3: Receive Packet-End Event (RPE). Set when the HDLC controller detects either the finish of a valid

message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC

checking error, or an overrun condition, or an abort has been seen. This is a latched bit and will be cleared when

read.

Bit 2: Receive Packet-Start Event (RPS). Set when the HDLC controller detects an opening byte. This is a

latched bit and will be cleared when read.

Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS). Set when the receive 64-byte FIFO crosses

the high watermark as defined by the Receive HDLC FIFO Control register (RHFC). Rising edge detect of RHWM.

Bit 0: Receive FIFO Not Empty Set Event (RNES). Set when the receive FIFO has transitioned from empty to not

empty (at least one byte has been put into the FIFO). Rising edge detect of RNE.

DS26521 Datasheet(PDF) 147 Page - Maxim Integrated Products