Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

DS26521 Datasheet(PDF) 218 Page - Maxim Integrated Products

Part # DS26521
Description  Single T1/E1/J1 Transceiver
PDF  258 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS26521 Datasheet(HTML) 218 Page - Maxim Integrated Products

Back Button DS26521 Datasheet HTML 214Page - Maxim Integrated Products DS26521 Datasheet HTML 215Page - Maxim Integrated Products DS26521 Datasheet HTML 216Page - Maxim Integrated Products DS26521 Datasheet HTML 217Page - Maxim Integrated Products DS26521 Datasheet HTML 218Page - Maxim Integrated Products DS26521 Datasheet HTML 219Page - Maxim Integrated Products DS26521 Datasheet HTML 220Page - Maxim Integrated Products DS26521 Datasheet HTML 221Page - Maxim Integrated Products DS26521 Datasheet HTML 222Page - Maxim Integrated Products Next Button
Zoom Inzoom in Zoom Outzoom out
 218 / 258 page
background image
DS26521 Single T1/E1/J1 Transceiver
218 of 258
Register Name:
BLSR
Register Description:
BERT Latched Status Register
Register Address:
110Eh
Bit #
7
6
5
4
3
2
1
0
Name
—
BBED
BBCO
BECO
BRA1
BRA0
BRLOS
BSYNC
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can create interrupts.
Bit 6: BERT Bit-Error-Detected Event (BBED). A latched bit that is set when a bit error is detected. The receive
BERT must be in synchronization for it to detect bit errors.
Bit 5: BERT Bit Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter
(BBC) overflows.
Bit 4: BERT Error Counter Overflow Event (BECO). A latched bit that is set when the 24-bit BERT error counter
(BEC) overflows.
Bit 3: BERT Receive All-Ones Condition (BRA1). A latched bit that is set when 32 consecutive ones are
received.
Bit 2: BERT Receive All-Zeros Condition (BRA0). A latched bit that is set when 32 consecutive zeros are
received.
Bit 1: BERT Receive Loss of Synchronization Condition (BRLOS). A latched bit that is set whenever the
receive BERT begins searching for a pattern.
Bit 0: BERT in Synchronization Condition (BSYNC). Will be set when the incoming pattern matches for 32
consecutive bit positions.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com