DS26521 datasheet(214/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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BC1

BERT Control Register 1

1105h

Bit #

Name

TINV

RINV

PS2

PS1

PS0

RESYNC

Default

Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to

be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be

cleared and set again for subsequent loads.

Bit 6:Transmit Invert Data Enable (TINV).

0 = do not invert the outgoing data stream

1 = invert the outgoing data stream

Bit 5:Receive Invert Data Enable (RINV).

0 = do not invert the incoming data stream

1 = invert the incoming data stream

Bits 4 to 2: Pattern Select Bits 2 to 0 (PS[2:0]). These bits select data pattern used by the transmit and receive

circuits. See Table 9-22.

Table 9-22. BERT Pattern Select

PS2

PS1

PS0

PATTERN DEFINITION

Pseudorandom 2E7-1

Pseudorandom 2E11-1

Pseudorandom 2E15-1

Pseudorandom Pattern QRSS. A 2

20 - 1 pattern with 14 consecutive zero restriction.

Repetitive Pattern

Alternating Word Pattern

Modified 55 Octet (Daly) Pattern. The Daly pattern is a repeating 55 octet pattern that is

byte-aligned into the active DS0 time slots. The pattern is defined in an ATIS (Alliance

for Telecommunications Industry Solutions) Committee T1 Technical Report Number 25

(November 1993).

Pseudorandom 2E-9-1

Bit 1: Load Bit and Error Counter (LC). A low-to-high transition latches the current bit and error counts into the

registers BBC1, BBC2, BBC3, BBC4 and BEC1, BEC2, and BEC3, and clears the internal count. This bit should be

toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set

again for subsequent loads.

Bit 0: Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to

resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes

to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.

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