GX1 datasheet(101/247 Pages) NSC

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Integrated Functions (Continued)

Table 4-4. L1 Cache BitBLT Register Summary

Mnemonic Name1

Function2

L1_BB0_BASE

L1 Cache BitBLT 0 Base Address

Contains the L1 set 0 address to the first byte of BLT Buffer 0.

L1_BB0_POINTER

L1 Cache BitBLT 0 Pointer

Contains the L1 set 0 address offset to the current line of BLT Buffer 0.

L1_BB1_BASE

L1 Cache BitBLT 1 Base Address

Contains the L1 set 0 address to the first byte of BLT Buffer 1.

L1_BB1_POINTER

L1 Cache BitBLT 1 Pointer

Contains the L1 set 0 address offset to the current line of BLT Buffer 1.

For information on accessing these registers, refer to Section 4.1.6 “CPU_READ/CPU_WRITE Instructions” on page

102.

The L1 cache locations accessed by the BitBLT registers must be enabled as scratchpad RAM prior to use.

Table 4-5. L1 Cache BitBLT Registers

Bit

Name

Description

L1_BB0_BASE Register (R/W)

Default Value = None

15:12

RSVD

Reserved: Set to 0.

11:4

INDEX

BitBLT 0 Base Index: The index to the starting cache line of set 0 in L1 of BLT Buffer 0.

3:0

BYTE

BitBLT 0 Starting Byte: Determines which byte of the starting line is the beginning of BLT Buffer 0.

L1_BB0_POINTER Register (R/W)

Default Value = None

15:12

RSVD

Reserved: Set to 0.

11:4

INDEX

BitBLT 0 Pointer Index: The index to the current cache line of set 0 in L1 of BLT Buffer 0.

3:0

RSVD

Reserved: Set to 0.

L1_BB1_Base Register (R/W)

Default Value = None

15:12

RSVD

Reserved: Set to 0.

11:4

INDEX

BitBLT 1 Base Index: The index to the starting cache line of set 0 in L1 of BLT Buffer 1.

3:0

BYTE

BitBLT 1 Starting Byte: Determines which byte of the starting line is the beginning of BLT Buffer 1.

L1_BB1_POINTER Register (R/W)

Default Value = None

15:12

RSVD

Reserved: Set to 0.

11:4

INDEX

BitBLT 1 Pointer Index: The index to the current cache line of set 0 in L1 of BLT Buffer 1.

3:0

RSVD

Reserved: Set to 0.

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