GX1 datasheet(105/247 Pages) NSC

105 / 247 page

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Integrated Functions (Continued)

SMID

SMID: All I/O accesses for address range 3D0h to 3DFh generate an SMI: 0 = Disable; 1 = Enable.

(Used for VGA virtualization.)

SMIC

SMIC: All I/O accesses for address range 3C0h to 3CFh generate an SMI: 0 = Disable; 1 = Enable.

(Used for VGA virtualization.)

SMIB

SMIB: All I/O accesses for address range 3B0h to 3BFh generate an SMI: 0 = Disable; 1 = Enable

(Used for VGA virtualization.)

12:8

RSVD

Reserved: Set to 0.

7XPD

X-Bus Pipeline: The address for the next cycle can be driven on the X-Bus before the completion of the

data phase of the current cycle.

0 = Enable

1 = Disable

6GNWS

X-Bus GraphicsPipeNo WaitState: Data driven on the X-Bus from the graphics pipeline:

0 = 1 full clock before X_DSX is asserted

1 = On the same clock in which X_RDY is asserted

5XNWS

X-Bus No Wait State: Data driven on the X-Bus from the internal bus interface unit:

0 = 1 full clock before X_DSX is asserted

1 = On the same clock in which X_RDY is asserted

4GEA

Graphics Enable for A Region: Allow memory R/W operations for address range B8000h to BFFFFh

be directed to the graphics pipeline: 0 = Disable; 1 = Enable. If enabled, the GEA region is always non-

cacheable. In the region control field (A0) the cache enable bit (bit2) is ignored.

(Used for VGA emulation.)

3:0

A0 Region: Region control field for address range A0000h to AFFFFh.

Note: Refer to Table 4-10 on page 106 for decode.

GX_BASE+8008h-800Bh

BC_XMAP_2 Register (R/W)

Default Value = 00000000h