GX1 datasheet(107/247 Pages) NSC

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Integrated Functions (Continued)

4.3

MEMORY CONTROLLER

The memory controller arbitrates requests from the X-Bus

(processor and PCI), display controller, and graphics pipe-

line. A total of 512 MB of SDRAM memory is supported.

The GX1 processor supports LVTTL (low voltage TTL)

technology. LVTTL technology allows the SDRAM interface

of the memory controller to run at frequencies up to 100

MHz.

TheSDRAMclock is afunctionofthe core clock. The

SDRAM bus can be run at speeds that range between 66

MHz and 100 MHz. The core clock can be divided down

from 2 to 5 in half clock increments to generate the SDRAM

clock. SDRAM frequencies between 79 MHz and 100 MHz

are only supported for certain types of closed systems and

strict design rules must be adhered to. For further details,

contact your local National Semiconductor technical sup-

port representative.

A basic block diagram of the memory controller is shown in

Figure 4-3.

Figure 4-3. Memory Controller Block Diagram

Address

Processor/PCI

Display Controller

Graphics Pipeline

Processor/PCI Address

Processor/PCI I/F

Display Controller I/F

Graphics Pipeline I/F

Arbiter

SDRAM

RASA#,RASB#

CKEA, CKEB

WEA#/WEB#

Configuration

MA[12:0]

BA[1:0]

Display Controller Address

Graphics Pipeline Address

Processor/PCI Data

Display Controller Data

Graphics Pipeline Data

Processor/PCI

Display Controller

MD[63:0]

Read Buffer

(16 Bytes)

Sequence

Controller

Timing

Controller

Registers

Control/MUX

Write Buffer (16 Bytes)

Graphics Controller

Write Buffer (16 Bytes)

Control

DQM[7:0]

CASA#,CASB#

CS[3:0]#

RFSH

Clock Divider

2, 2.5, 3, 3.5, 4, 4.5, 5

SDCLK[3:0]

Core Clock (ph2)

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