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Revision 1.0

Integrated Functions (Continued)

4.3.3

SDRAM Commands

This subsection discusses the SDRAM commands sup-

ported by the memory controller. Table 4-12 summarizes

these commands followed by detailed operational informa-

tion regarding each command. Refer to the SDRAM manu-

facturer’s specification for more information on component

banks..

MRS — The Mode Register Set command defines the spe-

cific mode of operation of the SDRAM. This definition

includes the selection of burst length, burst type, and CAS

latency. CAS latency is the delay, in clock cycles, between

the registration of a read command and the availability of

the first piece of output data.

The burst length is programmed by address bits MA[2:0],

the burst type by address bit MA3 and the CAS latency by

address bits MA[6:4].

The memory controller only supports a burst length of two

and burst type of interleave.

The field value on MA[12:0] and BA[1:0] during the MRS

cycle are as shown in Table 4-13.

PRE — The precharge command is used to deactivate the

open row in a particular component bank or the open row

in all (2 or 4, device dependent) component banks.

Address pin MA10 determines whether one or all compo-

nent banks are to be precharged. In the case where only

one component bank is to be precharged, BA[1:0] selects

which bank. Once a component bank has been pre-

charged, it is in the Idle state and must be activated prior to

any read or write commands.

Table 4-12. Basic Command Truth Table

Name

Command

RAS

CAS

MRS

Mode Register Set

PRE

Bank Precharge

ACT

Bank activate/row-

address entry

WRT

Column address

entry/Write opera-

tion

READ

Column address

entry/Read opera-

tion

DESL

Control input inhibit/

No operation

RFSH1

This command is CBR (CAS-before-RAS) refresh when CKE

is high and self refresh when CKE is low.

CBR Refresh or

Auto Refresh

Table 4-13. Address Line Programming during MRS Cycles

BA[1:0]

MA[12:7]

MA[6:4]

MA3

MA[2:0]

000000

CAS Latency:

000 = Reserved

010= 2CLK

100= 4CLK

110= 6CLK

001= 1CLK

011= 3CLK

101= 5CLK

111= 7CLK

Burst type is always

interleave.

001

Burst length is always 2.

128-bit transfer.

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