GX1 datasheet(112/247 Pages) NSC

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112

Revision 1.0

Integrated Functions (Continued)

4.3.4

Memory Controller Register Description

The Memory Controller maps 100h locations starting at

GX_BASE+8400h. Refer to Section 4.1.2 “Control Regis-

ters” on page 99 for instructions on accessing these regis-

ters.

Table 4-14 summarizes the 32-bit registers contained in the

memory controller. Table 4-15 gives detailed register/bit

formats.

Table 4-14. Memory Controller Register Summary

GX_BASE+

Memory Offset

Type

Name/Function

Default Value

8400h-8403h

R/W

MC_MEM_CNTRL1

Memory Controller Control Register 1: Memory controller configuration informa-

tion (e.g., refresh interval, SDCLK ratio, etc.). BIOS must program this register

based on the processor frequency and desired SDCLK divide ratio.

248C0040h

8404h-8407h

R/W

MC_MEM_CNTRL2

Memory Controller Control Register 2: Memory controller configuration informa-

tion to control SDCLK. BIOS must program this register based on the processor

frequency and the SDCLK divide ratio.

00000801h

8408h-840Bh

R/W

MC_BANK_CFG

Memory Controller Bank Configuration: Contains the configuration information for

the each of the four SDRAM banks in the memory array. BIOS must program this

41104110h

840Ch-840Fh

R/W

MC_SYNC_TIM1

Memory Controller Synchronous Timing Register 1: SDRAM memory timing infor-

mation - This register controls the memory timing of all four banks of DRAM.

BIOS must program this register based on the processor frequency and the

SDCLK divide ratio.

2A733225h

8414h-8417h

R/W

MC_GBASE_ADD

Memory Controller Graphics Base Address Register: This register sets the graph-

ics memory base address, which is programmable on 512 KB boundaries. The

display controller and the graphics pipeline generate a 20-bit DWORD offset that

is added to the graphics memory base address to form the physical memory

address. Typically, the graphics memory region is located at the top of physical

memory.

00000000h

8418h-841Bh

R/W

MC_DR_ADD

Memory Controller Dirty RAM Address Register: This register is used to set the

Dirty RAM address index for processor diagnostic access. This register should be

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