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Integrated Functions (Continued)

entry. Except for 8-bpp modes, all VGA configurations drive

four bits of pixel data into the palette, which produces a 6-

bit result. Based on various control registers, this value is

then combined with other register contents to produce an

8-bit index into the DAC. There is a ColorPlaneEnable reg-

ister to mask bits out of the pixel data before it goes to the

palette; this is used to emulate four-color CGA modes by

ignoring the top two bits of each pixel. In 8-bpp modes, the

palette is bypassed and the pixel data goes directly to the

DAC.

4.6.1.5

VGA Video BIOS

The video BIOS supports the VESA BIOS Extensions

(VBE) Version 1.2 and 2.0, as well as all standard VGA

BIOS calls. It interacts with Virtual VGA through the use of

several extended VGA registers. These are virtual registers

contained in the VSA code for Virtual VGA. (These regis-

ters are defined in a separate document.)

4.6.2

Virtual VGA

The GX1 processor reduces the burden of legacy hardware

by using a balanced mix of hardware and software to pro-

vide the same functionality. The graphics pipeline contains

full hardware support for the VGA “front-end”, the logic that

controls read and write operations to the VGA frame buffer

(located in graphics memory). For some modes, the hard-

ware can also provide direct display of the data in the VGA

buffer. Virtual VGA traps frame buffer accesses only when

necessary, but it must trap all VGA I/O accesses to main-

tain the VGA state and properly program the graphics pipe-

line and display controller.

The processor core contains SMI generation hardware for

VGA memory write operations. The bus controller contains

SMI generation hardware for VGA I/O read and write oper-

ations. The graphics pipeline contains hardware to detect

and process reads and writes to VGA memory. VGA mem-

ory is partitioned from system memory.

VGA functionality with the GX1 processor includes the

standard VGA modes (VGA, EGA, CGA, and MDA) as well

as the higher-resolution VESA modes. The CGA and MDA

modes (modes 0 through 7) require that Virtual VGA con-

vert thedatainthe VGAbuffer toaseparate 8-bppframe

buffer that the hardware can use for display refresh.

The remaining modes, VGA, EGA, and VESA, can be dis-

played directly by the hardware, with no data conversion

required. For these modes, Virtual VGA often outperforms

typical VGA cards because the frame buffer data does not

travel across an external bus.

Display drivers for popular GUI (graphical user interface)

based operating systems are provided by National Semi-

conductor which enable a full featured 2D hardware accel-

erator to be used instead of the emulated VGA core.

4.6.2.1

Datapath Elements

The graphics controller contains several elements that con-

vert between host data and frame buffer data.

The rotator simply rotates the byte written from the host by

0 to 7 bits to the right, based on the RotateCount field of

the DataRotate register. It has no effect in the read path.

The display latch is a 32-bit register that is loaded on every

read access to the frame buffer. All 32 bits of the frame

buffer DWORDs are loaded into the latch.

The write-mode unit converts a byte from the host into a

32-bit value. A VGA has four write modes:

• WriteMode0:

— Bit n of byte b comes from one of two places,

depending on bit b of the EnableSetReset register. If

that bit is zero, it comes from bit n of the host data. If

that bit is one, it comes from bit b of the SetReset

some planes from the host data and the others from

SetReset.

• WriteMode1:

— All 32 bits come directly out of the display latch; the

host data is ignored. This mode is used for screen-to-

screen copies.

• WriteMode2:

— Bit n of byte b comes from bit b of the host data; that

is, the four LSBs of the host data are each replicated

through a byte of the result. In conjunction with the

BitMask register, this mode allows the programmer to

directly write a 4-bit color to one or more pixels.

• WriteMode3:

— Bit n of byte b comes from bit b of the SetReset

below).

The read mode unit converts a 32-bit value from the frame

buffer into a byte. A VGA has two read modes:

• Read Mode 0:

— One of the four bytes from the frame buffer is

returned, based on the value of the ReadMapSelect

address select a plane. In odd/even read mode, bit 0

of the read address replaces bit 0 of ReadMapSelect.

• Read Mode 1:

— Bit n of the result is set to 1 if bit n in every byte b

matches bit b of the ColorCompare register; other-

wise it is set to 0. There is a ColorDon’tCare register

that can exclude planes from this comparison. In

four-plane graphics modes, this provides a conver-

sion from 4-bpp to 1-bpp.

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