GX1 datasheet(165/247 Pages) NSC

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Integrated Functions (Continued)

4.6.4

Virtual VGA Register Descriptions

This section describes the registers contained in the graph-

ics pipeline used for VGA emulation. The graphics pipeline

maps 200h locations starting at GX_BASE+8100h. Refer

to Section 4.1.2 “Control Registers” on page 99 for instruc-

tions on accessing these registers.

The registers are summarized in Table 4-38, followed by

detailed bit formats in Table 4-39.

Table 4-38. Virtual VGA Register Summary

GX_BASE+

Memory Offset

Type

Name/Function

Default Value

8140h-8143h

R/W

GP_VGA_WRITE

Graphics Pipeline VGA Write Patch Control register: Controls the VGA memory

write path in the graphics pipeline.

xxxxxxxxh

8144h-8147h

R/W

GP_VGA_READ

Graphics Pipeline VGA Read Patch Control register: Controls the VGA memory

read path in the graphics pipeline.

00000000h

8210h-8213h

R/W

GP_VGA_BASE VGA

Graphics Pipeline VGA Memory Base Address register: Specifies the offset of the

VGA memory, starting from the base of graphics memory.

xxxxxxxxh

8214h-8217h

R/W

GP_VGA_LATCH

Graphics Pipeline VGA Display Latch register : Provides a memory mapped way

to read or write the VGA display latch.

xxxxxxxxh

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