GX1 datasheet(166/247 Pages) NSC

166 / 247 page

www.national.com

166

Revision 1.0

Integrated Functions (Continued)

Table 4-39. Virtual VGA Registers

Bit

Name

Description

GX_BASE+8140h-8143h

GP_VGA_WRITE Register (R/W)

Default Value = xxxxxxxxh

31:28

RSVD

Reserved: Set to 0.

27:24

MAP_MASK

Map Mask: Enables planes 3 through 0 for writing. Combined with chain control to determine the

final enables.

23:21

RSVD

Reserved: Set to 0.

Write Mode 3: Selects write mode 3 by using the bit mask with the rotated data.

Write Mode 2: Selects write mode 2 by controlling set/reset.

18:16

Rotate Count: Controls the 8-bit rotator.

15:12

SRE

Set/Reset Enable: Enables the set/reset value for each plane.

11:8

Set/Reset: Selects 1 or 0 for each plane if enabled.

7:0

BIT_MASK

Bit Mask: Selects data from the data latches (last read data).

GX_BASE+8144h-8147h

GP_VGA_READ Register (R/W)

Default Value = 00000000h

31:18

RSVD

Reserved: Set to 0.

17:16

RMS

Read Map Select: Selects which plane to read in read mode 0 (Chain 2 and Chain 4 inactive).

F15

Force Address Bit 15: Forces address bit 15 to 0.

PC4

Packed Chain 4: Provides 64 KB of packed pixel addressing when used with Chain 4 mode. This bit

causes the VGA addresses to be shifted right by 2 bits.

Chain 4 Mode: Selects Chain 4 mode for both read operations and write operations. This overrides

bits 10 and 9 of this register.

Page Bit: Becomes LSB of address if COE is set high.

COE

Chain Odd/Even: Selects PB rather than A0 for least-significant VGA address bit.

Write Chain 2 Mode: Selects Chain 2 mode for write operations. Bit 13 overrides this bit.

9R2

Read Chain 2 Mode: Selects Chain 2 mode for read operations. Bit 13 overrides this bit.

8RM

Read Mode: Selects between read mode 0 (normal) and read mode 1 (color compare).

7:4

CCM

Color Compare Mask: Selects planes to include in the color comparison (read mode 1).

3:0

Color Compare: Specifies value of each plane for color comparison (read mode 1).

GX_BASE+8210h-8213h

GP_VGA_BASE (R/W)

Default Value = xxxxxxxxh

31:14

RSVD

Reserved: Set to 0.

13:8

VGA_RD_BASE

Read Base Address: The VGA base address is added to the graphics memory base to specify

where VGA memory starts. The VGA base address provides address bits [19:14] when mapping

VGA accesses into graphics memory. This allows the VGA base address to start on any 64 KB

boundary within the 4 MB of graphics memory. This register is used for reads to the VGA trace buffer.

7:6

RSVD

Reserved: Set to 0.

5:0

VGA_WR_BASE

Write Base Address: The VGA base address is added to the graphics memory base to specify

where VGA memory starts. The VGA base address provides address bits [19:14] when mapping

VGA accesses into graphics memory. This allows the VGA base address to start on any 64 KB

boundary within the 4 MB of graphics memory. This register is used for writes to the VGA trace buffer.

GX_BASE+8214h-8217h

GP_VGA_LATCH Register (R/W)

Default Value = xxxxxxxxh

31:0

LATCH

Display Latch: Specifies the value in the VGA display latch. VGA read operations cause VGA frame

buffer data to be latched in the display latch. VGA write operations can use the display latch as a

source of data for VGA frame buffer write operations.

GX1 Datasheet(PDF) 166 Page - National Semiconductor (TI)

GX1 Datasheet(HTML) 166 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL