GX1 datasheet(169/247 Pages) NSC

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Integrated Functions (Continued)

4.7.7

PCI Configuration Space Registers

To access the internal PCI configuration registers of the

GX1

processor,

the

Configuration

Address

(CONFIG_ADDRESS) must be written as a DWORD using

the format shown in Table 4-42. Any other size will be inter-

preted as an I/O write to Port 0CF8h. Also, when entering

the Configuration Index, only the six most significant bits of

the offset are used, and the two least significant bits must

be 00b.

Table 4-43 summarizes the registers located within the

Configuration Space. The tables that follow, give detailed

Table 4-42. Format for Accessing the Internal PCI Configuration Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

Reserved

000000000000000

Configuration Index

Table 4-43. PCI Configuration Space Register Summary

Index

Type

Name

Default Value

00h-01h

Vendor Identification

1078h

02h-03h

Device Identification

0001h

04h-05h

R/W

PCI Command

0007h

06h-07h

R/W

Device Status

0280h

08h

Revision Identification

00h

09h-0Bh

Class Code

060000h

0Ch

Cache Line Size

00h

0Dh

R/W

Latency Timer

00h

0Eh-3Fh

Reserved

00h

40h

R/W

PCI Control Function 1

00h

41h

R/W

PCI Control Function 2

96h

42h

Reserved

00h

43h

R/W

PCI Arbitration Control 1

80h

44h

R/W

PCI Arbitration Control 2

00h

45h-FFh

Reserved

00h

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