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168

Revision 1.0

Integrated Functions (Continued)

4.7.6

PCI Configuration Space Control

Registers

There

are

two

registers

this

category:

CONFIG_ADDRESS and CONFIG_DATA.

The CONFIG_ADDRESS register contains the address

information for the next configuration space access to

CONFIG_DATA. Only DWORD accesses are permitted to

this register all others will be forwarded as normal I/O

cycles to the PCI bus.

The CONFIG_DATA register contains the data that is sent

or received during a PCI configuration space access.

Table 4-41 gives the bit formats for these two registers.

Table 4-41. PCI Configuration Registers

Bit

Name

Description

I/O Offset 0CF8h-0CFBh

CONFIG_ADDRESS Register (R/W)

Default Value = 00000000h

CFG_EN

CONFIG ENABLE: Determines when accesses should be translated to configuration cycles on the

PCI bus, or treated as a normal I/O operation. This register will be updated only on full DWORD I/O

operations to the CONFIG_ADDRESS. Any other accesses are treated as normal I/O cycles in order

to allow I/O devices to use BYTE or WORD registers at the same address and remain unaffected.

Once bit 31 is set high, subsequent accesses to CONFIG_DATA are then translated to configuration

cycles.

1 = Generate configuration cycles.

0 = Normal I/O cycles.

30:24

RSVD

Reserved: Set to 0.

23:16

BUS

Bus: Specifies a PCI bus number in the hierarchy of 1 to 256 buses.

15:11

DEVICE

Device: Selects a device on a specified bus. A device value of 00h will select the GX1 processor if

the bus number is also 00h. DEVICE values of 01h to 15h will be mapped to AD[31:11], so only 21 of

the 32 possible devices are supported. A DEVICE value of 00001b will map to AD[11] while a device

of 10101b will map to AD[31].

10:8

FUNCTION

Function: Selects a function in a multi-function device.

7:2

1:0

Translation Type Bits: These bits indicate if the configuration access is local or one that requires

translation through other bridges to another PCI bus. When an access occurs to the CONFIG_DATA

address and the specified bus number matches the GX1 processor’s bus number (00h), then a Type

0 translation takes place.

For a Type 0 translation, the CONFIG_ADDRESS register values are translated to AD lines on the

PCI bus. Note that bits [10:2] are passed unchanged. The DEVICE value is mapped to one of 21 AD

lines. The translation type bits are set to 00 to indicate a transaction on the local PCI bus.

When an access occurs to the CONFIG_DATA address and the specified bus number is not 00h

(Type 1), the GX1 processor passes this cycle to the PCI bus by copying the contents of the

CONFIG_ADDRESS register onto the AD lines during the address phase of the cycle while driving

the translation type bits AD[1:0] to 01.

I/O Offset 0CFCh-0CFFh

CONFIG_DATA (R/W)

Default Value = 00000000h

31:0

CONFIG_DATA

Configuration Data register: Contains the data that is sent or received during a PCI configuration

space access. The register accessed is determined by the value in the CONFIG_ADDRESS register.

The CONFIG_DATA register supports BYTE, WORD, or DWORD accesses. To access this register,

bit 31 of the CONFIG_ADDRESS register must be set to 0 and a full DWORD I/O access must be

done. Configuration cycles are performed when bit 31 of the CONFIG_ADDRESS register is set to 1.

GX1 Datasheet(PDF) 168 Page - National Semiconductor (TI)

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