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Revision 1.0

Integrated Functions (Continued)

3SWBE

PCI Slave Write Buffer Enable: GX1 PCI slave write buffers: 0 = Disable; 1 = Enable.

2CLRE

PCI Cache Line Read Enable: Read operations from the PCI into the GX1 processor:

0 = Single cycle unless a read multiple or memory read line command is used.

1 = Cause a cache line read to occur.

1XBE

X-Bus Burst Enable: Enable X-Bus bursting when an external master performs PCI write/invalidate

cycles. 0 = Disable; 1 = Enable.

(This bit does not control read bursting; bit 2 does.)

0RSVD

Reserved: Should return a value of 0.

Index 41h

PCI Control Function 2 Register (R/W)

Default Value = 96h

7RSVD

Reserved: Set to 0.

6RW_CLK

Raw Clock: A debug signal used to view internal clock operation. 0 = Enable; 1 = Disable.

5PFS

PERR# forces SERR#: PCI master drives an active SERR# anytime it also drives or receives an active

PERR#: 0 = Disable; 1 = Enable.

4XWB

X-Bus to PCI Write Buffer: Enable GX1 processor PCI master’s X-Bus write buffers (non-locked mem-

ory cycles are buffered, I/O cycles and lock cycles are not buffered): 0 = Disable; 1 = Enable.

3:2

SDB

Slave Disconnect Boundary: GX1 as a PCI slave issues a disconnect with burst data when it crosses

line boundary:

00 = 128 bytes

01 = 256 bytes

10 = 512 bytes

11 = 1024 bytes

Works in conjunction with bit 1.

1SDBE

Slave Disconnect Boundary Enable: GX1 as a PCI slave:

0 = Disconnects on boundaries set by bits [3:2].

1 = Disconnects on cache line boundary which is 16 bytes.

0XWS

X-Bus Wait State Enable: The PCI slave acting as a master on the X-Bus will insert wait states on write

cycles for data setup time. 0 = Disable; 1 = Enable.

Index 42h

Reserved

Default Value = 00h

Index 43h

PCI Arbitration Control 1 Register (R/W)

Default Value = 80h

7BG

Bus Grant:

0 = Grants bus regardless of X-BUS buffers.

1 = Grants bus only if X-BUS buffers are empty.

6RSVD

Reserved: Set to 1.

5RME2

REQ2# Retry Mask Enable: Arbiter allows the REQ2# to be masked based on the master retry mask in

bits [2:1]: 0 = Disable; 1 = Enable.

4RME1

REQ1# Retry Mask Enable: Arbiter allows the REQ1# to be masked based on the master retry mask in

bits [2:1]: 0 = Disable; 1 = Enable.

3RME0

REQ0# Retry Mask Enable: Arbiter allows the REQ0# to be masked based on the master retry mask in

bits [2:1]: 0 = Disable; 1 = Enable.

2:1

MRM

Master Retry Mask: When a target issues a retry to a master, the arbiter can mask the request from the

retried master in order to allow other lower order masters to gain access to the PCI bus:

00 = No retry mask

01 = Mask for 16 PCI clocks

10 = Mask for 32 PCI clocks

11 = Mask for 64 PCI clocks

0HXR

Hold X-bus on Retries: Arbiter holds the X-Bus X_HOLD for two additional clocks to see if the retried

master will request the bus again: 0 = Disable; 1 = Enable

(This may prevent retry thrashing in some cases.)

Table 4-44. PCI Configuration Registers (Continued)

Bit

Name

Description

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