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170

Revision 1.0

Integrated Functions (Continued)

Table 4-44. PCI Configuration Registers

Bit

Name

Description

Index 00h-01h

Vendor Identification Register (RO)

Default Value = 1078h

31:0

VID (RO)

Vendor Identification register (Read Only): The combination of this value and the device ID uniquely

identifies any PCI device. The Vendor ID is the ID given to National Semiconductor Corporation by the

PCI SIG.

Index 02h-03h

Device Identification Register (RO)

Default Value = 0001h

31:0

DIR (RO)

Device Identification register (Read Only): This value along with the vendor ID uniquely identifies any

PCI device.

Index 04h-05h

PCI Command Register (R/W)

Default Value = 0007h

15:10

RSVD

Reserved: Set to 0.

9FBE

Fast Back-to-Back Enable (RO): As a master, the GX1 processor does not support this function.

This bit returns 0.

8SERR

SERR# Enable: This is used as an output enable gate for the SERR# driver.

7WAT

Wait Cycle Control: GX1 processor does not do address/data stepping.

This bit is always set to 0.

6PE

Parity Error Response:

0 = GX1 processor ignores parity errors on the PCI bus.

1 = GX1 processor checks for parity errors.

5VPS

VGA Palette Snoop: GX1 processor does not support this function.

This bit is always set to 0.

4MS

Memory Write and Invalidate Enable: As a master, the GX1 processor does not support this function.

This bit is always set to 0.

3SPC

Special Cycles: GX1 processor does not respond to special cycles on the PCI bus.

This bit is always set to 0.

2BM

Bus Master:

0 = GX1 processor does not perform master cycles on the PCI bus.

1 = GX1 processor can act as a bus master on the PCI bus.

1MS

Memory Space: GX1 processor will always respond to memory cycles on the PCI bus.

This bit is always set to 1.

IOS

I/O Space: GX1 processor will not respond to I/O accesses from the PCI bus.

This bit is always set to 1.

Index 06h-07h

PCI Device Status Register (RO, R/W Clear)

Default Value = 0280h

DPE

Detected Parity Error: When a parity error is detected, this bit is set to 1.

This bit can be cleared to 0 by writing a 1 to it.

SSE

Signaled System Error: This bit is set whenever SERR# is driven active.

RMA

Received Master Abort: This bit is set whenever a master abort cycle occurs. A master abort will occur

whenever a PCI cycle is not claimed except for special cycles.

This bit can be cleared to 0 by writing a 1 to it.

RTA

Received Target Abort: This bit is set whenever a target abort is received while the GX1 processor is

master of the cycle.

This bit can be cleared to 0 by writing a 1 to it.

STA

Signaled Target Abort: This bit is set whenever the GX1 processor signals a target abort. A target abort

is signaled when an address parity occurs for an address that hits in the GX1 processor’s address space.

This bit can be cleared to 0 by writing a 1 to it.

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