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GX1 Datasheet(PDF) 227 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 227 Page - National Semiconductor (TI) |
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227 / 247 page  Revision 1.0 227 www.national.com Instruction Set (Continued) JMP Unconditional Jump 8-bit Displacement EB + -------- 1 1 b h,j,k,r Full Displacement E9 +++ 1 1 Register/Memory Indirect Within Segment FF [mod 100 r/m] 1/3 1/3 Direct Intersegment -Call Gate Same Privilege Level -16-bit Task to 16-bit TSS -16-bit Task to 32-bit TSS -16-bit Task to V86 Task -32-bit Task to 16-bit TSS -32-bit Task to 32-bit TSS -32-bit Task to V86 Task EA [unsigned full offset, selector] 812 22 186 192 126 189 195 129 Indirect Intersegment -Call Gate Same Privilege Level -16-bit Task to 16-bit TSS -16-bit Task to 32-bit TSS -16-bit Task to V86 Task -32-bit Task to 16-bit TSS -32-bit Task to 32-bit TSS -32-bit Task to V86 Task FF [mod 101 r/m] 10 13 23 187 193 127 190 196 130 JNB/JAE/JNC Jump on Not Below/Above or Equal/Not Carry 8-bit Displacement 73 + -------- 1 1 r Full Displacement 0F 83 +++ 1 1 JNBE/JA Jump on Not Below or Equal/Above 8-bit Displacement 77 + -------- 1 1 r Full Displacement 0F 87 +++ 1 1 JNE/JNZ Jump on Not Equal/Not Zero 8-bit Displacement 75 + -------- 1 1 r Full Displacement 0F 85 +++ 1 1 JNL/JGE Jump on Not Less/Greater or Equal 8-bit Displacement 7D + -------- 1 1 r Full Displacement 0F 8D +++ 1 1 JNLE/JG Jump on Not Less or Equal/Greater 8-bit Displacement 7F + -------- 1 1 r Full Displacement 0F 8F +++ 1 1 JNO Jump on Not Overflow 8-bit Displacement 71 + -------- 1 1 r Full Displacement 0F 81 +++ 1 1 JNP/JPO Jump on Not Parity/Parity Odd 8-bit Displacement 7B + -------- 1 1 r Full Displacement 0F 8B +++ 1 1 JNS Jump on Not Sign 8-bit Displacement 79 + -------- 1 1 r Full Displacement 0F 89 +++ 1 1 JO Jump on Overflow 8-bit Displacement 70 + -------- 1 1 r Full Displacement 0F 80 +++ 1 1 JP/JPE Jump on Parity/Parity Even 8-bit Displacement 7A + -------- 1 1 r Full Displacement 0F 8A +++ 1 1 JS Jump on Sign 8-bit Displacement 78 + -------- 1 1 r Full Displacement 0F 88 +++ 1 1 LAHF Load AH with Flags 9F --------- 2 2 LAR Load Access Rights From Register/Memory 0F 02 [mod reg r/m] -----x --- 9 a g,h,j,p LDS Load Pointer to DS C5 [mod reg r/m] --------- 4 9 b h,i,j Table 8-27. Processor Core Instruction Set Summary (Continued) Instruction Opcode Flags Real Mode Prot’d Mode Real Mode Prot’d Mode OD I T S Z A P C FFFFFFFFF Clock Count (Reg/Cache Hit) Issues |
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