LM93 datasheet(21/95 Pages) TI1

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LM93

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SNAS210E – DECEMBER 2003 – REVISED MARCH 2013

3.15.2 DIGITAL NOISE EFFECT ON SMBUS COMMUNICATION

Noise coupling into the digital lines (greater than 150mV), overshoot greater than VDD and undershoot less

than GND, may prevent successful SMBus communication with the LM93. SMBus No Acknowledge

(NACK) is the most common symptom, causing unnecessary traffic on the bus. Although, the SMBus

maximum frequency of communication is rather low (100 kHz max), care still needs to be taken to ensure

proper termination within a system with multiple parts on the bus and long printed circuit board traces. The

LM93 includes on chip low-pass filtering of the SMBCLK and SMBDAT signals to make it more noise

immune. Minimize noise coupling by keeping digital traces out of switching baseboard areas as well as

ensuring that digital lines containing high speed data communications cross at right angles to the

SMBDAT and SMBCLK lines.

3.15.3 GENERAL SMBUS TIMING

The SMBus 2.0 specification defines specific conditions for different types of read and write operations but

in general the SMBus protocol operates as follows:

The master initiates data transfer by establishing a START condition, defined as a high to low transition on

the serial data line SMBDAT while the serial clock line SMBCLK remains high. This indicates that a data

stream follows. All slave peripherals connected to the serial bus respond to the START condition, and shift

in the next 8 bits. This consists of a 7-bit slave address (MSB first) plus a R/W bit, which determines the

direction of the data transfer, i.e. whether data is written to or read from the slave device (0 = write, 1 =

read).

The peripheral whose address corresponds to the transmitted address responds by pulling the data line

low during the low period before the ninth clock pulse, known as the Acknowledge Bit, and holding it low

during the high period of this clock pulse. All other devices on the bus now remain idle while the selected

device waits for data to be read from or written to it. If the R/W bit is a 0 then the master writes to the

slave device. If the R/W bit is a 1 the master reads from the slave device.

Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge

bit. Data transitions on the data line must occur during the low period of the clock signal and remain stable

during the high period, as a low to high transition when the clock is high may be interpreted as a STOP

signal.

If the operation is a write operation, the first data byte after the slave address is a command byte. This

tells the slave device what to expect next. It may be an instruction, such as telling the slave device to

expect a block write, or it may simply be a register address that tells the slave where subsequent data is

to be written.

Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command

to a slave device during a read operation. Before doing a read operation, it is necessary to do a write

operation to tell the slave what sort of read operation to expect and/or the address from which data is to

be read.

When all data bytes have been read or written, stop conditions are established. In WRITE mode, the

master will allow the data line to go high during the 10th clock pulse to assert a STOP condition. In READ

mode, the slave drives the data not the master. For the bit in question, the slave is looking for an

acknowledge and the master doesn't drive low. This is known as ‘No Acknowledge’. The master then

takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock

pulse to assert a STOP condition.

Note, a repeated START may be given only between a write and read operation that are in succession.

Functional Description

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