LM93 datasheet(72/95 Pages) TI1

72 / 95 page

LM93

SNAS210E – DECEMBER 2003 – REVISED MARCH 2013

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Bit

Name

R/W

Description

ZN1

R/W

If set, PWM2 will be bound to temperature zone 1.

ZN2

R/W

If set, PWM2 will be bound to temperature zone 2.

ZN3

R/W

If set, PWM2 will be bound to temperature zone 3.

ZN4

R/W

If set, PWM2 will be bound to temperature zone 4.

PH1

R/W

If set, PWM2 will be bound to P1_PROCHOT.

PH2

R/W

If set, PWM2 will be bound to P2_PROCHOT.

VRD1

R/W

If set, PWM2 will be bound to VRD1_HOT.

VRD2

R/W

If set, PWM2 will be bound to VRD2_HOT.

This register can bind PWM2 to several different control sources. The temperature zones control the PWM

duty cycle using the table lookup function. The Px_PROCHOT and VRDx_HOT inputs control the PWM

using the ramp up/ramp down functions. If multiple control sources are bound to PWM2, the largest duty

cycle being requested will be used.

3.17.8.18 Register CDh

PWM2 Control 2

Read/

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

Write

Name

Value

PWM2

EPPL

INV

OVR

CDh

R/W

OVR_DC

00h

Control 2

Bit

Name

R/W

Description

OVR

R/W

When set, enables manual duty cycle override for PWM2.

INV

R/W

Invert PWM1 output. When 0, 100% duty cycle corresponds to the PWM output

continuously HIGH. When 1, 100% duty cycle corresponds to the PWM output

continuously LOW.

EPPL

R/W

Enable PROCHOT PWM2 lock. When set, this bit causes bound PROCHOT events

on PWM2 to trigger PPL (bit [3]). When cleared, PPL never gets set.

PPL

R/W

PROCHOT PWM2 lock. When set, this bit indicates that PWM2 is currently being

held at 100% because a bound PROCHOT event occurred while EPPL (bit [2]) was

set. This bit is cleared by writing a zero. Clearing this bit allows the fans to return to

normal operation. This bit is not locked by the LOCK bit in the LM93 Configuration

7:4

OVR_DC

R/W

This field sets the duty cycle that will be used by PWM2 whenever manual override

mode is active. This field accepts 16 possible values that are mapped to duty cycles

according the table in the FAN CONTROL section. Whenever this register is read, it

returns the duty cycle that is currently being used by PWM2 regardless of whether

override mode is active or not. The value read may not match the last value written

if another control source is requesting a greater duty cycle. This field always returns

0h when the PWM2 spin up cycle is active.

3.17.8.19 Register CEh

PWM2 Control 3

Read/

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

Write

Name

Value

PWM2

RES

SU_DC

CEh

R/W

SU_DUR

00h

Control 3

Bit

Name

R/W

Description

3:0

SU_DC

R/W

This field sets the duty cycle that used whenever PWM2 experiences a Spin-Up

cycle. This field accepts 16 possible values that are mapped to duty cycles

according the table in the Auto-Fan Control section. Setting this field to 0h effectively

disables Spin-Up.

RES

Reserved

7:5

SU_DUR

R/W

Sets the Spin-Up duration for PWM2.

Bits 7:5 configure the spin-up duration. When the duty cycle of PWM2 changes from zero to a non-zero

value, the spin-up sequence is activated for the specified amount of time. The available settings are

defined according to this table:

SPACER

Functional Description

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