LM93 datasheet(84/95 Pages) TI1

84 / 95 page

LM93

SNAS210E – DECEMBER 2003 – REVISED MARCH 2013

www.ti.com

4.4

AC Electrical Characteristics

The following limits apply for +3.0 VDC to +3.6 VDC, unless otherwise noted. Bold face limits apply for TA = TJ = TMIN to TMAX

of the operating range; all other limits TA = TJ = 25°C unless otherwire noted.

Typical

Limits

Units

Symbol

Parameter

Conditions

(1)

(2)

(Limits)

FAN RPM-TO-DIGITAL CHARACTERISTICS

Counter Resolution

bits

Number of fan tach pulses count is based

pulses

Counter Frequency

22.5

kHz

Accuracy

±6

% (max)

PWM OUTPUT CHARACTERISTICS

Frequency Tolerances

±6

% (max)

Duty-Cycle Tolerance

±2

±6

% (max)

RESET INPUT/OUTPUT CHARACTERISTICS

Output Pulse Width

250

ms (min)

Upon Power Up

330

ms (max)

Minimum Input Pulse Width

µs (min)

Reset Output Fall Time

1.6V to 0.4V Logic Levels

µs (max)

SMBUS TIMING CHARACTERISTICS(3)

fSMBCLK

SMBCLK (Clock) Clock Frequency

kHz (min)

100

kHz (max)

tBUF

SMBus Free Time between Stop and

4.7

µs (min)

Start Conditions

tHD;STA

Hold time after (Repeated) Start

Condition. After this period, the first clock

4.0

µs (min)

is generated.

tSU;STA

Repeated Start Condition Setup Time

4.7

µs (min)

tSU;STO

Stop Condition Setup Time

4.0

µs (min)

tSU;DAT

Data Input Setup Time to SMBCLK High

250

ns (min)

tHD;DAT

Data Output Hold Time after SMBCLK

300

ns (min)

Low

930

ns (max)

tLOW

SMBCLK Low Period

4.7

µs (min)

µs (max)

tHIGH

SMBCLK High Period

4.0

µs (min)

µs (max)

Rise Time

µs (max)

Fall Time

300

ns (max)

tTIMEOUT

Timeout

SMBDAT or SMBCLK low

ms (min)

time required to

ms (max)

reset the Serial Bus

Interface to the Idle State

tPOR

Time in which a device must be

VDD > +2.8V

500

ms (max)

operational after power-on reset

Capacitance Load on SMBCLK and

400

pF (max)

SMBDAT

(1)

Typical parameters are at TJ = TA = 25 °C and represent most likely parametric norm.

(2)

Limits are specified to TI's AOQL (Average Outgoing Quality Level).

(3)

Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output

voltage is forced to 1.4V.

Electrical Specifications

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