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LM93 Datasheet(PDF) 49 Page - Texas Instruments |
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LM93 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 95 page  LM93 www.ti.com SNAS210E – DECEMBER 2003 – REVISED MARCH 2013 Sleep Bit Name R/W Description Masking 3 AD12_ERR RWC This bit is set when the AD_IN12 voltage has fallen outside the range defined by S3*, S4/5* the AD_IN12 Low Limit and the AD_IN12 High Limit registers. 4 AD13_ERR RWC This bit is set when the AD_IN13 voltage has fallen outside the range defined by S3*, S4/5* the AD_IN13 Low Limit and the AD_IN13 High Limit registers. 5 AD14_ERR RWC This bit is set when the AD_IN14 voltage has fallen outside the range defined by S3*, S4/5* the AD_IN14 Low Limit and the AD_IN14 High Limit registers. 6 AD15_ERR RWC This bit is set when the AD_IN15 voltage has fallen outside the range defined by S3, S4/5 the AD_IN15 Low Limit and the AD_IN15 High Limit registers. 7 AD16_ERR RWC This bit is set when the AD_IN16 voltage has fallen outside the range defined by none the AD_IN16 Low Limit and the AD_IN16 High Limit registers. 3.17.4.4 Register 43h B_Error Status 4 Register Read/ Register Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address Write Name Value B_Error D2_ D1_ DVDDP2 DVDDP1 SCSI2 SCSI1 43h RWC RES 00h Status 4 ERR ERR _ERR _ERR _ERR _ERR Sleep Bit Name R/W Description Masking 1:0 RES R Reserved N/A 2 SCSI1_ERR RWC SCSI Fuse Error S3, S4/5 This bit is set if SCSI_TERM1 has been asserted. 3 SCSI2_ERR RWC SCSI Fuse Error S3, S4/5 This bit is set if SCSI_TERM2 has been asserted. 4 DVDDP1_ERR RWC Dynamic Vccp Limit Error. S3, S4/5 This bit is set if AD_IN7 (P1_Vccp) did not match the requested voltage as reported by P1_VID[5:0]. 5 DVDDP2_ERR RWC Dynamic Vccp Limit Error. S3, S4/5 This bit is set if AD_IN8 (P2_Vccp) did not match the requested voltage as reported by P1_VID[5:0]. 6 D1_ERR RWC Diode Fault Error S3*, S4/5* This bit is set if there is an open or short circuit on the REMOTE1+ and REMOTE1 − pins. 7 D2_ERR RWC Diode Fault Error S3*, S4/5* This bit is set if there is an open or short circuit on the REMOTE2+ and REMOTE2 − pins. 3.17.4.5 Register 44h B_P1_PROCHOT Error Status Register Read/ Register Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address Write Name Value B_P1_PR TMAX OCHOT PH1 44h RWC T100 T75 T50 T25 T12 T0 00h Error _ERR Status Sleep Bit Name R/W Description Masking 0 T0 RWC Set when P1_PROCHOT has had a throttled event. This bit is set for any amount S3, S4/5 of PROCHOT throttling >0%. 1 T12 RWC Set when P1_PROCHOT has throttled greater than or equal to 0.39% but less than S3, S4/5 12.5%. 2 T25 RWC Set when P1_PROCHOT has throttled greater than or equal to 12.5% but less than S3, S4/5 25%. 3 T50 RWC Set when P1_PROCHOT has throttled greater than or equal to 25% but less than S3, S4/5 50%. 4 T75 RWC Set when P1_PROCHOT has throttled greater than or equal to 50% but less than S3, S4/5 75%. 5 T100 RWC Set when P1_PROCHOT has throttled greater than or equal to 75% but less than S3, S4/5 100%. Copyright © 2003–2013, Texas Instruments Incorporated Functional Description 49 Submit Documentation Feedback Product Folder Links: LM93 |
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