LM93 datasheet(6/95 Pages) TI1

6 / 95 page

LM93

SNAS210E – DECEMBER 2003 – REVISED MARCH 2013

www.ti.com

Table 2-1. Pin Descriptions(1) (continued)

Symbol

Pin #

Type

Function

AD_IN2

Analog Input (+12V2)

Analog Input for +12V Rail 2 monitoring, for CPU2 voltage regulator. External

attenuation resistors required such that 12V is attenuated to 0.927V.

AD_IN3

Analog Input (+12V3)

Analog Input for +12V Rail 3, for Memory/3GIO slots. External attenuation

resistors required such that 12V is attenuated to 0.927V.

AD_IN4

Analog Input (FSB_Vtt)

Analog input for 1.2V monitoring

AD_IN5

Analog Input (3GIO /

Analog input for 1.5V monitoring.

PXH / MCH_Core)

AD_IN6

Analog Input

Analog input for 1.5V monitoring.

(ICH_Core)

AD_IN7 (P1_Vccp)

Analog Input

Analog input for +Vccp (processor voltage) monitoring.

(CPU1_Vccp)

AD_IN8 (P2_Vccp)

Analog Input

Analog input for +Vccp (processor voltage) monitoring.

(CPU2_Vccp)

AD_IN9

Analog Input (+3.3V)

Analog input for +3.3V monitoring.

AD_IN10

Analog Input (+5V)

Analog input for +5V monitoring silver box supply monitoring.

AD_IN11

Analog Input

Analog input for +2.5V monitoring.

(SCSI_Core)

AD_IN12

Analog Input

Analog input for +1.969V monitoring.

(Mem_Core)

AD_IN13

Analog Input

Analog input for +0.984V monitoring.

(Mem_Vtt)

AD_IN14

Analog Input

Analog input for +0.984V S/B monitoring.

(Gbit_Core)

AD_IN15

Analog Input (-12V)

Analog input for -12V monitoring. External resistors required to scale to

positive level. Full scale reading at 1.236V.

Address Select

3 level analog input

This input selects the lower two bits of the LM93 SMBus slave address.

AD_IN16

POWER (VDD) +3.3V

VDD power input for LM93. Generally this is connected to +3.3V standby

standby power

power.

The LM93 can be powered by +3.3V if monitoring in low power states is not

required, but power should be applied to this input before any other pins.

This pin also serves as the analog input to monitor the 3.3V stand-by (SB)

voltage. It is necessary to bypass this pin with a 0.1 µF in parallel with 100

pF. A bulk capacitance of 10 µF should be in the near vicinity. The 100 pF

should be closest to the power pin.

GND

GROUND

Digital Ground. Digital ground and analog ground need to be tied together at

the chip then both taken to a low noise system ground. A voltage difference

between analog and digital ground may cause erroneous results.

PWM1

Digital Output (Open-

Fan control output 1.

Drain)

PWM2

Digital Output (Open-

Fan control output 2

Drain)

P1_VID0

Digital Input

Voltage Identification signal from the processor.

P1_VID1

Digital Input

Voltage Identification signal from the processor.

P1_VID2

Digital Input

Voltage Identification signal from the processor.

P1_VID3

Digital Input

Voltage Identification signal from the processor.

P1_VID4

Digital Input

Voltage Identification signal from the processor.

P1_VID5

Digital Input

Voltage Identification signal from the processor.

P1_PROCHOT

Digital I/O (Open-Drain) Connected to CPU1 PROCHOT (processor hot) signal through a bidirectional

level shifter.

P2_PROCHOT

Digital I/O (Open-Drain) Connected to CPU2 PROCHOT (processor hot) signal through a bi-

directional level shifter.

P2_VID0

Digital Input

Voltage Identification signal from the processor.

P2_VID1

Digital Input

Voltage Identification signal from the processor.

P2_VID2

Digital Input

Voltage Identification signal from the processor.

P2_VID3

Digital Input

Voltage Identification signal from the processor.

Device Information

Submit Documentation Feedback

Product Folder Links: LM93

LM93 Datasheet(PDF) 6 Page - Texas Instruments

LM93 Datasheet(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

Datasheet Download

Link URL