LM93 datasheet(75/95 Pages) TI1

75 / 95 page

LM93

www.ti.com

SNAS210E – DECEMBER 2003 – REVISED MARCH 2013

If a TACH channel is bound to a PWM channel, TACH errors on that channel are automatically masked

when the bound PWM is at 0% duty cycle or performing spin-up. Behavior is undefined if a TACH channel

is bound to both PWM outputs. This register must be setup when Smart Tach Mode is enabled in register

BDh, Special Function Control 2.

3.17.8.24 Register E2h

LM93 Status Control

Read/

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

Write

Name

Value

LM93 Status/

BMC

HOST

TACH_EDGE

GPI5_A

GPI4_AM

ASF

OVRID

E2h

R/W

00h

Control

_ERR

Lock

Bit

Name

R/W

Description

OVRID

R/W

If this bit is set, all PWM outputs go to 100% duty cycle.

ASF

R/W

If this bit is set, BMC error registers support ASF, i.e. reset on read. When

not in ASF mode, a write “1” is required to clear the bits in the BMC error

status registers.

GPI4_AM

R/W

GPI4 Auto Mask Enable

If this bit is set, an error event on GPI4 causes all other error events to be

masked.

The BMC Error Status registers do not reflect any new error events until the

GPI4_ERR bit is cleared in the B_GPI Error Status register. The HOST Error

Status registers do not reflect any new error events until the GPI4_ERR bit

is cleared in the H_GPI Error Status register.

If a CPU_THERMTRIP signal is connected to GPIO4, this ensures that

unwanted error events do not fire once CPU_THERMTRIP is asserted.

GP15_AM

R/W

GPI5 Auto Mask Enable

This bit works exactly the same as GPI4_AM, but applies to GPI5.

5:4

TACH_EDGE

R/W

This field determines what type of edges are used for measuring fan tach

pulses. This effects all four tachometer inputs.

HOST_ERR

This bit gets set if any error bit is set in any of the Host Error Status registers

(H_).

BMC_ERR

This bit gets set if any error bit is set in any of the BMC Error Status

registers (B_). When this bit is set, ALERT are asserted if enabled.

SPACER

Edge Type Used for

TACH_EDGE

Tachometer Measurements

Either rising or falling edges may be

used.

Rising edges only

Falling edges only

Reserved

3.17.8.25 Register E3h

LM93 Configuration

Read/

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

Write

Name

Value

LM93

RES

P1P2_

ALERT

GMSK

LOCK

START

E3h

R/W

Configura

READY

PROCHO

_EN

00h

tion

Lock

Bit

Name

R/W

Description

START

R/W

When this bit is 0, the LM93 operates in basic mode. All error events are

masked. The auto fan control algorithm is disabled. Both PWMs are set to

0%, but the Fan Boost function operates based on default limits. All

monitoring functions are active and the value registers are updated.

Once this bit is set, error events are no longer globally masked, and the

auto-fan control algorithm is enabled. Fan boost uses the programmed

values instead of the defaults.

It is expected that all limit and setup registers are set by BIOS or application

software prior to setting this bit.

Functional Description

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