LM93 datasheet(29/95 Pages) TI1

29 / 95 page

LM93

www.ti.com

SNAS210E – DECEMBER 2003 – REVISED MARCH 2013

Slave

Fixed

Slave

Byte

Data

Address

Block

Address

Count

Byte 1

Byte N

Command

(N)

Code

(F2h–FDh)

Special Notes:

1. The LM93 returns 00h when address locations outside of normal address space are read.

2. Block reads do not wrap around from address FFh to 00h.

3. If the master acknowledges more bytes that it requested, the LM93 continues to supply data until the

master does not acknowledge a byte.

4. If the master does not acknowledges a byte to prematurely abort a block read, the LM93 gets off the

bus to allow the master to issue a STOP signal.

3.15.5.4.6 I2C Block Reads

The LM93 supports I2C block reads. The following sequence of events occur in this transaction:

1. The master sends a START to start this transaction .

2. The master send 7-bit slave address followed by a write bit (low).

3. The slave asserts an ACK.

4. The master sends the register address and the slave asserts an ACK.

5. The master sends a repeated START.

6. The master sends the 7-bit slave address followed by a read bit (high).

7. The slave asserts an ACK.

8. The master receives Data Byte 1 and asserts an ACK.

9. The master continues to receive bytes and asserting an ACK for each byte received.

10. The master receives the last byte.

11. The master asserts a NACK.

12. The master issues a STOP.

SPACER

Slave

Data

Address

Byte 1

Byte 2

Byte N

Special Notes:

1. The LM93 returns 00h when address locations outside of normal address space are read.

2. Block reads do not wrap around from address FFh to 00h.

3. If the master acknowledges more bytes that it requested, the LM93 continues to supply data until the

master does not acknowledge a byte.

4. If the master does not acknowledges a byte to prematurely abort a block read, the LM93 gets off the

bus to allow the master to issue a STOP signal.

3.15.6 READING AND WRITING 16-BIT REGISTERS

Whenever the low byte of a 16-bit register is read, the high byte is frozen. After the high byte is read, it is

unfrozen. This ensures that the entire 16-bit value is read properly and the high byte matches with the low

byte. If the low byte of a different 16-bit register is read, the currently frozen high byte is unfrozen and the

high byte of the new 16-bit register is frozen. In a system with two SMBus masters, it is very important that

only one master reads any 16-bit registers at a time. One possible method to achieve this would involve

using 16-bit SMBus reads (instead of two separate 8-bit reads) to read 16-bit registers.

Functional Description

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